Electronic digital logic circuitry – Multifunctional or programmable – Sequential or with flip-flop
Reexamination Certificate
2007-02-20
2007-02-20
Tran, Anh Q. (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Sequential or with flip-flop
C326S038000, C326S040000
Reexamination Certificate
active
10850978
ABSTRACT:
A programmable finite state machine (FSM) includes, in part, a first address calculation logic block, a first lookup table, a second address calculation logic block, and a second lookup table. The first address calculation logic block generates an address for the first lookup table based on the received input symbol and the current state. The data stored in first look-up table at the generated address is used by the second address calculation logic block to compute an address for the second lookup table. Data stored in the second lookup table is the next state to which the FSM transitions. The programmable FSMs uses redundant information of the transition table to compress these transitions and thus requires a smaller memory while maintaining a high data throughput. The data in the first and second lookup tables are coded and supplied by a compiler. The FSM operation may optionally be pipelined.
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Barrie Robert Matthew
Flanagan Michael
Gould Stephen
Peltzer Ernest
Williams Darren
Sensory Networks, Inc.
Townsend and Townsend / and Crew LLP
Tran Anh Q.
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