Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-03-17
2001-08-21
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C326S021000
Reexamination Certificate
active
06279145
ABSTRACT:
BRIEF DESCRIPTION OF THE INVENTION
This invention relates generally to noise isolation in integrated circuits. More particularly, this invention relates to a circuit that prevents overshoot and undershoot signals on an input node from generating internal glitch signals on an output node of a circuit.
BACKGROUND OF THE INVENTION
Digital systems commonly operate in noisy conditions. Noisy conditions are usually defined as environments where there are signals unrelated to the signal of interest. In some cases, the noise content can be so large that false switching occurs. That is, noise can cause a digital low signal to appear as a digital high signal or vice versa.
On occasion, noise conditions cause erroneous signal glitches between circuit nodes that should otherwise be isolated. This problem is especially common in those cases where the two nodes are at times connected and at times disconnected by an isolation circuit, such as a multiplexer or pass transistor. For example, assume there is an input node that is supposed to be isolated from an output node with an n-channel pass transistor whose gate is grounded. The pass transistor will turn-on if the undershooting signal on the input node is more negative in magnitude than the Vtn of the pass transistor. Conversely, for a p-channel pass transistor, if the overshoot signal is greater than the Vtp of the pass transistor, it too will turn-on. In both cases, a signal glitch occurs on the output node that was supposed to be isolated.
In view of the foregoing, it would be highly desirable to provide an isolation circuit that prevents signal glitches in the presence of undershoot and overshoot signals. Ideally, such a circuit should be simple to implement and should otherwise be compatible with existing circuit designs.
SUMMARY OF THE INVENTION
The apparatus of the invention includes a circuit to reduce erroneous signal glitches in the presence of overshoot and undershoot signals. The circuit includes an output node and an input node that alternately receives overshoot and undershoot signals. A noise-vulnerable transistor is connected to the input node. An output isolation transistor is connected between the noise-vulnerable transistor and the output node. A pull-up transistor controls the charge state at a control node between the noise-vulnerable transistor and the isolation transistor, such that if the overshoot and undershoot signals cause the noise-vulnerable transistor to turn-on, the pull-up transistor establishes a charge state at the control node that keeps the output isolation transistor off and therefore isolates the output node from erroneous signal glitches.
The method of the invention includes the steps of receiving overshoot and undershoot signals. A noise-vulnerable transistor is turned-on in response to the overshoot and undershoot signals. The charge state at a node of an output isolation transistor is controlled in response to the turning-on step. As a result, the charge state keeps the output isolation transistor off and therefore isolates an output node from the overshoot and undershoot signals.
The technique of the invention limits the impact of noisy signals in integrated circuits. In particular, the invention prevents signal glitches in the presence of undershoot and overshoot signals. The circuit is simple to implement and is otherwise compatible with existing circuit designs.
REFERENCES:
patent: 5715408 (1998-02-01), Chidhambarakirshnan
patent: 6043702 (2000-03-01), Singh
patent: 6175952 (2001-01-01), Patel et al.
Altera Corporation
Garbowski Leigh Marie
Pennie & Edmonds LLP
Smith Matthew
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