Apparatus and method for invalidation of redundant branch...

Details Apparatus and method for invalidation of redundant branch... Apparatus and method for invalidation of redundant branch...

2006-12-19

2006-12-19

Fleming, Fritz (Department: 2181)

Electrical computers and digital processing systems: processing

Processing control

Branching

C712S237000

Reexamination Certificate

active

07152154

ABSTRACT:
An apparatus for invalidating redundant entries in an N-way set associative branch target address cache (BTAC) for the same branch instruction is disclosed. An index portion of an instruction cache fetch address is applied to the BTAC to select a set of N ways therein. Control logic detects a condition in which more than one of the N ways of the selected set has a valid tag that matches the tag portion of the fetch address. A flag is set to indicate the occurrence of the condition, and the fetch address is stored in a register. The control logic subsequently invalidates all but one of the N ways having a valid tag that matches the fetch address tag.

REFERENCES:
patent: 4181942 (1980-01-01), Forster et al.
patent: 4200927 (1980-04-01), Hughes et al.
patent: 4860197 (1989-08-01), Langendorf et al.
patent: 5142634 (1992-08-01), Fite et al.
patent: 5163140 (1992-11-01), Stiles et al.
patent: 5313634 (1994-05-01), Eickemeyer
patent: 5353421 (1994-10-01), Emma et al.
patent: 5355459 (1994-10-01), Matsuo et al.
patent: 5394530 (1995-02-01), Kitta
patent: 5404467 (1995-04-01), Saba et al.
patent: 5434985 (1995-07-01), Emma et al.
patent: 5513330 (1996-04-01), Stiles
patent: 5530825 (1996-06-01), Black et al.
patent: 5553246 (1996-09-01), Suzuki
patent: 5604877 (1997-02-01), Hoyt et al.
patent: 5623614 (1997-04-01), Van Dyke et al.
patent: 5623615 (1997-04-01), Salem et al.
patent: 5634103 (1997-05-01), Dietz et al.
patent: 5687349 (1997-11-01), McGarity
patent: 5687360 (1997-11-01), Chang
patent: 5706491 (1998-01-01), McMahan
patent: 5721855 (1998-02-01), Hinton et al.
patent: 5734881 (1998-03-01), White et al.
patent: 5752069 (1998-05-01), Roberts et al.
patent: 5761723 (1998-06-01), Black et al.
patent: 5768576 (1998-06-01), Hoyt et al.
patent: 5805877 (1998-09-01), Black et al.
patent: 5812839 (1998-09-01), Hoyt et al.
patent: 5828901 (1998-10-01), O'Toole et al.
patent: 5832289 (1998-11-01), Shaw et al.
patent: 5850532 (1998-12-01), Narayan et al.
patent: 5850543 (1998-12-01), Shiell et al.
patent: 5864707 (1999-01-01), Tran et al.
patent: 5867701 (1999-02-01), Brown et al.
patent: 5881260 (1999-03-01), Raje et al.
patent: 5881265 (1999-03-01), McFarland et al.
patent: 5931944 (1999-08-01), Ginosar et al.
patent: 5948100 (1999-09-01), Hsu et al.
patent: 5961629 (1999-10-01), Nguyen et al.
patent: 5964868 (1999-10-01), Gochman et al.
patent: 5968169 (1999-10-01), Pickett
patent: 5974543 (1999-10-01), Hilgendorf et al.
patent: 5978909 (1999-11-01), Lempel
patent: 6035391 (2000-03-01), Isaman
patent: 6041405 (2000-03-01), Green
patent: 6044459 (2000-03-01), Bae et al.
patent: 6081884 (2000-06-01), Miller
patent: 6085311 (2000-07-01), Narayan et al.
patent: 6088793 (2000-07-01), Liu et al.
patent: 6101595 (2000-08-01), Pickett et al.
patent: 6108773 (2000-08-01), Col et al.
patent: 6122729 (2000-09-01), Tran
patent: 6134654 (2000-10-01), Patel et al.
patent: 6151671 (2000-11-01), D'Sa et al.
patent: 6157988 (2000-12-01), Dowling
patent: 6170054 (2001-01-01), Poplingher
patent: 6175897 (2001-01-01), Ryan et al.
patent: 6185676 (2001-02-01), Poplingher et al.
patent: 6233676 (2001-05-01), Henry et al.
patent: 6250821 (2001-06-01), Schwendinger
patent: 6256727 (2001-07-01), McDonald
patent: 6260138 (2001-07-01), Harris
patent: 6279105 (2001-08-01), Konigsburg et al.
patent: 6279106 (2001-08-01), Roberts
patent: 6308259 (2001-10-01), Witt
patent: 6314514 (2001-11-01), McDonald
patent: 6321321 (2001-11-01), Johnson
patent: 6351796 (2002-02-01), McCormick et al.
patent: 6374350 (2002-04-01), D'Sa et al.
patent: 6457120 (2002-09-01), Sinharoy
patent: 6502185 (2002-12-01), Keller et al.
patent: 6560696 (2003-05-01), Hummel et al.
patent: 6601161 (2003-07-01), Rappoport et al.
patent: 6647467 (2003-11-01), Dowling
patent: 6725357 (2004-04-01), Cousin
patent: 6748441 (2004-06-01), Gemmell
patent: 6754808 (2004-06-01), Roth et al.
patent: 6823444 (2004-11-01), Henry et al.
patent: 6886093 (2005-04-01), Henry et al.
patent: 6895498 (2005-05-01), McDonald et al.
patent: 6898699 (2005-05-01), Jourdan et al.
patent: 6968444 (2005-11-01), Kroesche et al.
patent: 2002/0188833 (2002-12-01), Henry et al.
patent: 2002/0194460 (2002-12-01), Henry et al.
patent: 2002/0194461 (2002-12-01), Henry et al.
patent: 2002/0194464 (2002-12-01), Henry et al.
patent: 2004/0030866 (2004-02-01), McDonald
patent: 2004/0139301 (2004-07-01), McDonald
patent: 2004/0143709 (2004-07-01), McDonald
patent: 2004/0143727 (2004-07-01), McDonald
patent: 2005/0044343 (2005-02-01), Henry et al.
patent: 2005/0076193 (2005-04-01), Henry et al.
patent: 2005/0114636 (2005-05-01), McDonald et al.
patent: 2005/0132175 (2005-06-01), Henry et al.
patent: 2005/0198479 (2005-09-01), Bean et al.
patent: 2005/0198481 (2005-09-01), Henry et al.
Eberly, Potter and Rossbach; The Correlation Branch Target Address Cache; May 1, 1996.
David A. Patterson and John L. Hennessy, Computer Organization & Design The Hardware/Software Interface, 1998.
Microprocessor Report. vol. 9. No. 2. Feb. 16, 1996, p. 5.
Microprocessor Report. Aug. 23, 1999. p. 7.
Yeh et al.Alternative Implementation of Two-Level Adaptive Branch Prediction. 19th Annual International Symposium on Computer Architecture. pp. 124-134. May 19-21, 1992. Gold Coast, Australia.
Chang et al.Alternative Implementations of Hybrid Branch Predictors. Proceedings of MICRO-28. 1995. IEEE.
Mc Farling, Scott.WRL Technical Note TN-36. Combining Branch Predictors. Jun. 1993. Western Research Laboratory, 250 University Ave., Palo Alto, CA 94301.
Bray et al.Strategies For Branch Target Buffers. Technical Report No. CSL-TR-91-480. Jun. 1991.
Sakamoto et al.Microarchitecture Support for Reducing Branch Penalty in a Superscaler Processor. pp. 208-216. Mittsubishi Electric Corp. 4-1 Mizuhara, Itami, Hyogo 664. Japan, 1996. IEEE.
IEEE 100, The Authoritative Dictionary of IEEE Standard Terms, Seventh Edition. The Institute of Electrical Engineering, Inc. New York: Standards Information Network IEEE Press p. 135.
Online Computing Dictionary. http://instantweb.com/d/dictionary/foldoc.cgi?query=btb May 5, 1995. Branch Target Buffer.
The D Latch, Play-Hookey Web Page, Oct. 10, 1999.
Patterson et al. “Computer Organization & Design: The Hardware/Software Interface.”Morgan Kaufmann Publishers, Inc. San Francisco, CA. 1998 p. 469.
Jimenez et al. “The Impact of Delay on the Design of the Branch Predictors.”2000.
IBM Technical Disclosure Bulletin NN9204269, “Return Address Stack Cache.” Apr. 1992, pp. 269-271.

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