Apparatus and method for interrupt control

Electrical computers and digital data processing systems: input/ – Interrupt processing

Reexamination Certificate

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C710S261000, C710S264000, C710S266000, C710S268000, C710S269000

Reexamination Certificate

active

10995175

ABSTRACT:
An interrupt control apparatus comprising an interrupt vector register for holding address information corresponding to interrupt resources of a first type which are managed by an operating system and interrupt resources of a second type which are not managed by the operating system. Regarding an interrupt generated by an interrupt resource of the first type, the interrupt control apparatus in the present invention launches a common interrupt entry function which is subject to a scheduling process common to the interrupt resources of the first type, based on the address information of the interrupt vector register. At the same time, with regard to an interrupt generated by an interrupt resource of the second type, the interrupt control apparatus in the present invention launches an extended interrupt entry function which is not subject to the aforementioned scheduling process, based on the address information held in the interrupt vector register.

REFERENCES:
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patent: 5768599 (1998-06-01), Yokomizo
patent: 5875341 (1999-02-01), Blank et al.
patent: 6038661 (2000-03-01), Yoshioka et al.
patent: 6112273 (2000-08-01), Kau et al.
patent: 6425038 (2002-07-01), Sprecher
patent: 6539447 (2003-03-01), Sawada
patent: 6968412 (2005-11-01), Nalawadi
patent: 2001-216172 (2001-08-01), None
Definition of Interrupt from Wikipedia.
Definition of Interrupt Descriptor Table from Wikipedia.
Definition of Interrupt Vector Table from Wikipedia.

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