Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
2006-09-29
2010-02-09
Lee, Thomas (Department: 2115)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C365S200000, C365S219000, C365S223000
Reexamination Certificate
active
07661010
ABSTRACT:
A delay locked loop (DLL) is added to the system in order to provide an accurate, PVT insensitive translation of the drive clocks into the write data eye. Adding a master-slave DLL to the system provides an accurate, PVT insensitive translation of the echo clocks into the read data eye. Solidifying the timing critical drive and receive logic which directly interfaces to the I/O buffers reduces the pin-to-pin skews. Utilizing clock phase outputs of the DLL in the solidified drive and receive logic blocks reduces further the skew between the clock and related data signals, and also removes the reliance on a differential clock. The system allows a much more relaxed constraint on clock duty cycle. Design of circuitry within the solidified drive and receive logic blocks permits simple logic modeling for fit within an ASIC flow. Physical design of the solidified drive and receive logic blocks permits simple fit within ASIC place and route flows for increased ease of implementation and ease of reuse.
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Becca Oswald
DeFazio Jody
Nyasulu Peter
Eaton Peabody Patent Group LLC
Haszko Dennis R.
Lee Thomas
Mosaid Technologies Incorporated
Tran Vincent T
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