Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-10-31
1999-06-29
Cabeca, John W.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711125, 3642617, 364938, 364948, G06F 932
Patent
active
059180447
ABSTRACT:
In an instruction fetch unit for an information handling system which decodes instructions, calculates target addresses of multiple branch instructions, and resolves multiple branch instructions in parallel instead of sequentially, the critical path through a multiple way set associative instruction cache is through a directory and compare circuit which selects which way instructions will be retrieved. This patch is known as the late select path. A multi-ported effective address (EA) directory is provided and is accessed prior to selection of a fetch address which fetches the next set of instructions from the cache. In this manner, the time required for the late select path can be reduced.
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Levitan David Stephen
Muhich John Stephen
Cabeca John W.
Dillon Andrew J.
England Anthony V.S.
Graham John G.
International Business Machines - Corporation
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