Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-06-10
2002-10-08
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06463574
ABSTRACT:
BRIEF DESCRIPTION OF THE INVENTION
This invention relates generally to the design of complex integrated circuits. More particularly, this invention relates to a technique for selecting an optimal distance between repeaters in a complex integrated circuit, and subsequently inserting repeaters into the complex integrated circuit based upon this optimal distance.
BACKGROUND OF THE INVENTION
Complex integrated circuits, such as Very Large Scale Integrated (VLSI) circuits, include relatively long signal paths. Signal repeaters are used in such circuits to mitigate the effect of signal propagation delays along these long signal paths. That is, after the layout of a complex integrated circuit is defined, repeater are inserted into the circuit to mitigate the effect of signal propagation delays along long signal paths.
Signal propagation over the on chip metal interconnect is significant due to Resistive-Capacitive (RC) delay. In general, the interconnect delay increases with the square of the length of the line. Delay is reduced through the use of repeaters, which are typically implemented as inverter or non-inverting buffers. There are certain objectives when inserting repeaters into a complex circuit. These objectives include the minimization of interconnect delay, limiting transition times, minimizing die area, and minimizing power consumption.
Standard practice is to analyze the interconnect network using rules-of-thumb, inserting repeaters in a simulated netlist model of the circuit (e.g., a SPICE simulated netlist model), and then simulating the network to analyze the solution. An observed general rule is to space repeaters evenly at intervals less than some maximum distance, which is determined through simulation. This general rule does not take into consideration networks with more than one receiver or branches or the effects of the receiver input capacitance or driver strength variations, thus additional analysis is needed to determine the optimum repeater location for specific networks. This procedure is repeated until a satisfactory solution is found which minimizes the interconnect delay and/or transition times. In a large scale microprocessor, the number of interconnect networks requiring this type of analysis is very large and would therefore require significant time and resources to complete.
A Resistive-Capacitive delay or Elmore delay is described in P. Penfield and J. Rubinstein, “Signal Delay in RC Tree Networks”, in
Proc
. 18
th
Design Automation Conf
., 1981, pp-613-617. The Elmore delay is an efficient way of calculating the delay for an RC tree. A first order approximation of RC delay at any node i on an RC tree is given by the Elmore time constant:
T
i
=
∑
k
=
1
n
R
ki
C
i
(
Equation
1
)
where R
ki
is the resistance of the portion of the (unique) path between the input and node i, which is common with the (unique) path between the input and node k, and Ck is the capacitance at node k.
The first order approximation of the waveform at node i is
V
i
(t)=
V
DD
(1−
e
−t/T
′) (Equation 2)
where Ti is the time constant Elmore delay given by Equation 1. The time at which the voltage at node i reaches any value V
x
is determined by
T
x
=
T
i
ln
V
DD
V
DD
-
V
x
(
Equation
3
)
A quick approximation of 20-80% (or 10-90%) transition time can be calculated by substituting Vx with voltages at 20 and 80% of V
DD
T
1
≈0.72
·T
20-80
(Equation 4)
The ratio coefficient of the transition time (20-80%) based on first order approximation is about 1.39 (i.e., 1/0.72).
The ratio coefficient based upon a first order approximation is not accurate enough for many repeater insertion methodologies. The reason for this is that the optimum distance between repeaters, and the size of the repeater itself that will satisfy design requirements are determined by running circuit simulations (e.g., SPICE simulations). The circuit simulations have at least some inherent inaccuracies. Accordingly, it would be highly desirable to identify a technique that minimizes the impact of circuit simulation inaccuracies, while simultaneously exploiting Elmore delay information. Such a technique could then be used for positioning repeaters in a complex integrated circuit.
SUMMARY OF THE INVENTION
A method of inserting repeaters into a complex integrated circuit includes the step of selecting, based upon signal transition data, a maximum wire length to be positioned between two repeaters in a complex integrated circuit. The maximum wire length is then correlated with a signal transition-based ratio coefficient defining the relation between a signal transition time and a Resistive-Capacitive delay. A signal transition-based Resistive-Capacitive delay is then defined based upon the signal transition-based ratio coefficient. A repeater distribution is then mapped within the complex integrated circuit based upon the signal transition-based Resistive-Capacitive delay.
The apparatus of the invention is a computer readable memory to direct a computer to function in a specified manner. The computer readable memory includes a wire length identification module to select, based upon signal transition data, a maximum wire length to be positioned between two repeaters in a complex integrated circuit. A ratio coefficient selection module correlates the maximum wire length with a signal transition-based ratio coefficient defining the relation between a signal transition time and a Resistive-Capacitive delay. A delay calculation module defines a signal transition-based Resistive-Capacitive delay based upon the signal transition-based ratio coefficient. A repeater insertion module maps a repeater distribution within the complex integrated circuit based upon the signal transition-based Resistive-Capacitive delay.
The invention uses an improved Resistive-Capacitive delay value that is based upon signal transition time information. The signal transition time information is incorporated into the Resistive-Capacitive delay value via the signal transition-based ratio coefficient. The more accurate Resistive-Capacitive value utilized in accordance with the invention results in the use of fewer repeaters. Accordingly, die size and power consumption is reduced.
REFERENCES:
patent: 5638291 (1997-06-01), Li et al.
patent: 5798935 (1998-08-01), Doreswamy et al.
patent: 6253359 (2001-06-01), Cano et al.
Amir Chaim
Culetu Julian
Levin Naum
Pennie & Edmonds LLP
Smith Matthew
Sun Microsystems Inc.
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