Electrical computers and digital data processing systems: input/ – Interrupt processing – Programmable interrupt processing
Reexamination Certificate
1997-12-31
2001-10-02
Pan, Daniel H. (Department: 2183)
Electrical computers and digital data processing systems: input/
Interrupt processing
Programmable interrupt processing
C710S264000, C710S267000, C710S261000, C710S262000, C712S032000
Reexamination Certificate
active
06298410
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to computers. More particularly, it relates to interrupt controllers for controlling interrupts in a computer.
2. Description of the Related Art
A computer is a machine that essentially does three things. First, it accepts input. Second, it processes the input according to a prescribed set of rules. Third, it produces as output the results of processing the input according to the prescribed set of rules.
To perform these tasks, a computer, in general, includes: an input device, such as a keyboard, that accepts input; and output device, such as a printer or video display, that outputs the results; and a processor, such as a central processing unit (CPU), that does the processing. In present-day personal computers, the CPU might be a microprocessor. Additionally, the computer might have memory. Such memory might be used by the processor to store data. Or the memory might be used to store computer instructions, which instructions were put into the memory in the form of microcode.
While the computer is operating and the processor is processing the input previously received by the computer according to the prescribed set of rules, the processor might receive a request for attention. For example, the processor might receive a request from the keyboard to accept new input. Such a request for attention is called an interrupt.
In general, when the processor receives an interrupt it suspends its current operations, saves the status of its work, and transfers control to a special routine which contains the instructions for dealing with the particular situation that caused the interrupt. Interrupts might be generated by various hardware devices to request service or to report problems, or by the processor itself in response to program errors or requests for operating system services. Interrupts are the processor's way of communicating with the other elements that make up the computer system. A hierarchy of interrupt priorities determines which interrupt request will be handled first, if more than one request has been made. Particular programs can temporarily disable some interrupts, when the program needs the full attention of the processor to complete a particular task.
In general, an interrupt can be considered a feature of a computer that permits the execution of one program to be interrupted in order to execute another program. That other program might be a special program that is executed when a specific interrupt occurs, sometimes called an interrupt handler. Interrupts from different causes have different handlers to carry out the corresponding tasks, such as updating the system clock or reading the keyboard. A table stored in memory contains pointers, sometimes called address vectors, that direct the processor to the various interrupt handlers. Programmers can create interrupt handlers to replace or supplement existing handlers. Alternatively, that other program might be one that takes place only when requested by means of an interrupt, sometimes called an interrupt-driven process. After the required task has been completed, the CPU is then free to perform other tasks until the next interrupt occurs. Interrupt driven processors sometimes are used to respond to such events as a floppy-disk drive having become ready to transfer data.
In general, computers include a hardware line, sometimes called an interrupt request line, over which devices such as a keyboard or a disk drive can send interrupts to the CPU. Such interrupt request lines are built into the computer's internal hardware, and are assigned different levels of priority so that the CPU can determine the sources and relative importance of incoming service requests.
The manner in which a particular computer deals with interrupts, is determined by the computer's interrupt controller. Early interrupt controllers were hard-wired in the computer. As such, their operation was fixed by the computer manufacturer, and could not be altered.
In certain sophisticated modern microprocessors, such as the PentiumPRO™ microprocessor manufactured by Intel, an advanced programmable interrupt controller is included in the CPU. This advanced programmable interrupt controller, referred to as APIC, is programmable. From a programmer's point of view, however, the APIC is viewed as an add-on because the APIC registers, even though they reside in the CPU, are accessed as a memory mapped device. That is, these APIC registers are written to, and read from, under the control of microcode, in the same manner as memory containing data or instructions.
The present invention provides a streamline advanced programmable interrupt controller (SAPIC) having an interrupt vector register (IVR) located in the CPU, which is not treated like computer memory, and which does not need microcode for control. The present invention eliminates the need for microcode for the interrupt controller, thereby eliminating the need for a costly on-chip read only memory (ROM) to carry that microcode. As a result, the portion of the chip formally devoted to such a microcode ROM can be used to implement more intelligent logic, thereby giving the chip maker a greater return on investment.
Nearly all known prior art programmable interrupt controllers are controlled by microcode. The microcode is coded by the microprocessor manufacturer, and thereafter cannot readily be changed by programmers to better meet the needs of, for example, a particular computer operating system. Consequentially, programmers cannot readily change the way in which interrupt control is carried out in the computer.
In the remaining known prior art devices, microprocessor manufacturers have implemented the entire interrupt management for the CPU in software, with no hardware implementation whatsoever. While this has eliminated interrupt controller microcode and the ROM to store such code, and does permit programmers to make changes to the control software, this approach has numerous disadvantages. For example, this approach results in more code that has to be executed by the processor every time an interrupt is encountered, thereby increasing the latency of interrupt servicing.
The present invention provides a more optimum solution, and is directed to overcoming, or at least reducing, the effects of one or more of the problems mentioned.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a register-based programmable interrupt controller is provided for controlling interrupts in a computer. The controller includes programmable software located in the CPU that controls when the pending interrupt having highest priority is provided, and hardware interrupt logic that controls how that pending highest priority interrupt is provided.
An interrupt vector register is included in the CPU. This register, however, does not act like the typical register. It is not a physical register, and cannot be written to. A read to this register, by the programmable software, triggers the hardware interrupt logic; once triggered, this logic performs certain control actions, the end result of which is returning to the programmable software a vector corresponding to the interrupt having highest priority. Thus the programmable software performs a read operation, and receives back data; that data, however, does not come from the register being read, but rather is generated by the hardware interrupt logic.
Known prior art devices have two types of registers: registers which have no side effect; and registers which have a side effect when a write is issued to the register. No known prior art registers perform a control activity, such as the priority management activity of the present invention, when a read is issued to the register.
According to an aspect of the present invention, the control actions performed by the hardware interrupt logic include determining if a non-maskable interrupt is present and, if so, returning to the programmable software an indication of that. If a non-maskable interrupt is not present, and if
Eakambaram Ravi
Goru Vijay Kumar
Jayakumar Muthurajan
Blakely, Sokoloff, Taylor & Zafamn LLP
Intel Corporation
Pan Daniel H.
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