Excavating
Patent
1996-02-27
1998-05-26
Beausoliel, Jr., Robert W.
Excavating
39518208, 371 671, 371 681, G06F 1116, G06F 1118, G06F 702
Patent
active
057580588
ABSTRACT:
A method and apparatus for initializing both processors in a master/checker fault detecting microprocessor. A microcode initialization routine is run by each processor upon reset of both of the processors in the pair. The routines cause each processor to be initialized, such that the two processors complete initialization at the same time and operate in a lock-step manner.
REFERENCES:
patent: 4176258 (1979-11-01), Jackson
patent: 4785453 (1988-11-01), Chandran et al.
patent: 4792955 (1988-12-01), Johnson et al.
patent: 4860196 (1989-08-01), Wengert
patent: 4903270 (1990-02-01), Johnson et al.
patent: 4916695 (1990-04-01), Ossfeldt
patent: 4937741 (1990-06-01), Harper et al.
patent: 4975831 (1990-12-01), Nilsson et al.
patent: 5054026 (1991-10-01), Tsubota
patent: 5115511 (1992-05-01), Nilsson et al.
patent: 5136595 (1992-08-01), Kimura
patent: 5157780 (1992-10-01), Stewart et al.
patent: 5226152 (1993-07-01), Klug et al.
patent: 5233615 (1993-08-01), Goetz
patent: 5410710 (1995-04-01), Sarangdhar et al.
Beausoliel, Jr. Robert W.
Intel Corporation
Vales P.
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