Boots – shoes – and leggings
Patent
1989-03-20
1992-09-29
Chan, Eddie P.
Boots, shoes, and leggings
395550, 364DIG1, 3642401, 36424292, 3642646, 3642718, G06F 1336, G06F 1342
Patent
active
051519798
ABSTRACT:
A data processing system consists of a number of processing modules and memory modules interconnected by a common bus. If a memory module is not free to accept addresses or data from the bus, it asserts an address wait (AW) signal or a data wait (DW) signal, as the case may be. When a processing module sends an address or data over the bus, it normally holds it there for one clock cycle only. However, if the relevant wait signal AW or DW is asserted, the address or data is held on the bus until this wait signal is removed. This arrangement avoids the need for acknowledgement on the bus, and hence speeds up the transaction of information.
REFERENCES:
patent: 4045782 (1977-08-01), Anderson
patent: 4807109 (1989-02-01), Farrel et al.
patent: 4853847 (1989-08-01), Ohuchi
patent: 4908749 (1990-03-01), Marshall et al.
patent: 4961140 (1990-10-01), Pechanek et al.
European Search Report.
Baron, "Stopping system memory and bus from putting the squeeze on fast CPUs", Electronics International, vol. 56, No. 19 (1983).
Sweazey, "Cache memory means faster access, multiple microprocessors", Electronic Design, vol. 34, No. 21 (Sep. 1986).
Chan Eddie P.
International Computers Limited
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