Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Patent
1996-05-24
1999-03-30
Westin, Edward P.
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
326 24, H03K 19096, H03K 1716
Patent
active
058894179
ABSTRACT:
A dynamic logic signal repeater includes a complementary dynamic logic circuit with an input node to receive an input signal and an output node storing a precharge signal. The complementary dynamic logic circuit configuration, transistor sizing, and the use of a precharge driver results in a signal transition trip point for the precharge signal on the output node that is substantially equivalent to the signal transition trip point of a static logic circuit. Thus, the dynamic logic signal repeater has improved noise immunity. An evaluation locking transistor is connected to the complementary dynamic logic circuit and the output node. The evaluation locking transistor prevents the charging of the output node during a dynamic logic evaluation period.
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Amir Chaim
Klass Edgardo F.
Poole David W.
Rogers Alan C.
Galliani William S.
Roseen Richard
Sun Microsystems Inc.
Westin Edward P.
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