Apparatus and method for improving bus usage in a system having

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area

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Details

711105, 711150, G06F 1206, G11C 11401

Patent

active

060556099

ABSTRACT:
A circuit suitable for use in electronic systems which utilize Synchronous Dynamic Random Access Memory (SDRAM), and method according to the present invention comprises an application-specific integrated circuit. When a burst command is initiated by the memory controller, causing the SDRAM to perform a data transfer into or out of memory which require many consecutive clock cycles to complete, the circuit recognizes the SDRAM commands as those commands appear on the instruction bus. The circuit then analyzes other operations which are pending and which might be performed during otherwise unusable time periods while the burst operation is being performed by the SDRAM. The circuit issues instructions to initiate and complete these operations prior to the SDRAM command being completed.

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