Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Patent
1996-05-16
1998-06-02
Coleman, Eric
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
711169, G06F 1300
Patent
active
057617368
ABSTRACT:
A state machine has states of three types: a fully scaled state, a partially scaled state and an unscaled state. The state machine (1) waits in the unscaled state for a minimum duration, (2) waits in the fully scaled state for a maximum duration that is a multiple of the minimum duration, and (3) waits in the partially scaled state for a duration smaller than the maximum duration but no smaller than the minimum duration. The state machine is included in a microprocessor chip, and is used to access an off-chip cache coupled to the microprocessor chip. The minimum and maximum durations are inverse of the respective clock frequencies of the microprocessor chip and of the off-chip cache. During a read access operation, the state machine waits in a partially scaled state while driving address signals of a to-be-retrieved word on an external bus coupled to the off-chip cache. Thereafter, the state machine waits in the fully scaled state on the external bus to access data signals driven by the off-chip cache to indicate the retrieved word. So, the state machine saves time by using the partially scaled state to set up address signals for a duration less than the maximum duration. Similarly, during a write access operation, the state machine also uses the partially scaled state to drive address signals and data signals of a to-be-written word to the off-chip cache.
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patent: 5596741 (1997-01-01), Thome
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Favor John Gregory
Sharma Puneet
Advanced Micro Devices , Inc.
Coleman Eric
Gunnison Forrest E.
Suryadevara Omkar K.
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