Apparatus and method for implementing multiple memory...

Details Apparatus and method for implementing multiple memory... Apparatus and method for implementing multiple memory...

2006-06-27

2006-06-27

Mai, Son (Department: 2827)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S189070, C365S233100

Reexamination Certificate

active

07068554

ABSTRACT:
A memory redundancy control apparatus includes a static compare stage configured to compare bits of a requested memory address to corresponding fuse information bits representing a defective memory address. A dynamic stage is configured to receive outputs of the static compare stage, with an output of the dynamic stage being precharged so as to initially deactivate primary subarray decoding circuitry. The dynamic stage is further triggered by a clock signal thereto. Upon activation of the clock signal, the output of the dynamic stage remains precharged whenever a match exists between the requested memory address and the defective memory address, and the output of the dynamic stage is discharged whenever a mismatch exists between the requested memory address and the defective memory address. A delay tracking clock generator is configured to generate a delay tracking clock signal with respect to the dynamic stage, to gate the output of the dynamic stage to spare subarray decoding circuitry, wherein the spare subarray decoding circuitry is activated whenever the output of the dynamic stage remains precharged following activation of the clock signal.

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