Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2000-05-05
2003-12-16
Baderman, Scott (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S733000
Reexamination Certificate
active
06665817
ABSTRACT:
BRIEF DESCRIPTION OF THE INVENTION
This invention relates generally to wireless communications. More particularly, this invention relates to a wireless communications system implemented on a single chip, which includes a reprogrammable tester, debugger, and bus monitor.
BACKGROUND OF THE INVENTION
A substantial obstacle to implementing a wireless communications system on a single chip is the problem of testing and debugging such an embedded system. Testing of a system-on-a-chip ensures the integrity of the manufacturing process by identifying manufacturing faults through the use of well-defined vector sets applied to the chip after production. These vectors can be defined using several techniques, such as ATPG (Automatic Test Pattern Generation), embedded logic BIST (Built-in-Self-Test) or embedded RAM BIST. The type of technique selected dictates the use of a specific hardware structure to implement the testing function.
Debugging of embedded software within embedded processors requires additional hardware resources to enable single-cycle execution, instruction insertion and break pointing techniques. Hardware resources that are required to support these functions are typically dedicated solely to these functions.
Another function required for today's embedded wireless systems is the ability to monitor the traffic which occurs on an embedded, shared system bus. Today, the function is usually implemented with dedicated hardware structures which “snoop” for and record specific types of bus transactions. This information can then be exported and used to tune the bus bandwidth requirements of the system.
Thus, current techniques to test, debug and monitor an embedded processor require dedicated hardware and are limited in capability. Accordingly, it would be highly desirable to provide a technique for testing, debugging, and bus monitoring of a wireless communications system-on-a-chip.
SUMMARY OF THE INVENTION
A wireless communication system-on-a-chip comprises a system bus, a set of fixed function processors connected to the system bus, an embedded processor connected to the system bus, and reconfigurable logic connected to the system bus. The reconfigurable logic supports an operational mode and a diagnostic mode. In the operational mode, the system operates to support different air interface protocols and data rates. In the diagnostic mode, the system alternately tests the system, debugs the system, and monitors bus activity within the system.
The invention includes a reconfigurable controller with a configuration and test controller and reconfigurable logic. The reconfigurable logic supports testing operations in a first mode, debugging operations in a second mode, and bus monitoring operations in a third mode.
The invention uses a reprogrammable fabric for a multitude of temporal functions which occur at different times in the product life cycle. Testing occurs at the time of manufacturing, debugging occurs during bring-up, and bus monitoring may occur to tune the system performance over the life of the product. By leveraging the same reconfigurable logic on the chip, all these functions are implemented in the same logic, assuming the proper signal interfaces are defined prior to production.
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Baderman Scott
Darby & Darby
Morphics Technology Inc.
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