Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1998-01-30
2002-01-22
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S133000, C711S144000, C711S148000
Reexamination Certificate
active
06341337
ABSTRACT:
BRIEF DESCRIPTION OF THE INVENTION
The present invention relates generally to memories in computer systems. More particularly, the invention relates to a snoop mechanism for use in a bus-based cache coherent multiprocessor system.
BACKGROUND OF THE INVENTION
Modem computer systems utilize various technologies and architectural features to achieve high performance operation. One such technology employs several central processing units (CPUS) or processors arranged in a multiprocessor configuration. In addition to the processor units such a multiprocessor system can include several I/O modules and a memory module, all coupled to one another by a system bus. The capabilities of the overall system can be enhanced by providing a cache memory at each of the processor units in the multiprocessor system.
Cache memories are used to improve system performance. A cache memory is a relatively small, fast memory which resides between a central processor and main system memory. Whenever the processor reads data in the cache memory, the time required to access the main system memory is avoided. Thus, a cache memory improves system performance.
In a multiprocessor system, the capability of the system can be enhanced by sharing memory among the various processors in the system and by operating the system bus in accordance with a snooping bus protocol. The snooping bus protocol is used to maintain cache coherency. In shared memory multiprocessor systems, it is necessary that the system store a single correct copy of data being processed by the various processors of the system. Thus, when a processor writes to a particular data item stored in its cache, that copy of the data item becomes the latest correct value for the data item. The corresponding data item stored in main memory, as well as copies of the data item stored in other caches in the system, becomes outdated or invalid.
The snooping protocol provides the necessary cache coherency between the various cache memories and main memory. In accordance with the snooping protocol, each processor monitors or snoops the bus for bus activity involving addresses of data items that are currently stored in the processor's cache memory. Status bits are maintained in a tag memory associated with each cache to indicate the status of each data item currently stored in the cache. A processor looks up each address in its cache memory, determines if it is there, and determines the appropriate action to take in response to the snooped command and address. The cache coherency protocol dictates the manner in which the state of the cache line is maintained in each cache memory and which processor provides the requested data.
One such cache coherency protocol is the MOSEI protocol which is associated with the following five cache tag states:
Exclusive Modified (M): the data block stored in the cache line corresponding to this tag has been modified by the data processor coupled to the cache and is not stored in any other cache memories.
Shared Modified (O): the data block stored in the cache line corresponding to this tag has been modified by the data processor coupled to this cache and may be stored in one or more other cache memories.
Exclusive Clean (E): the data block stored in the cache line corresponding to this tag has not been modified by the data processor coupled to this cache and is not stored in any other cache memories.
Shared Clean (S): the data block stored in the cache line corresponding to this tag has not been modified by the processor coupled to the cache, and the cache line can be stored in one or more other cache memories.
Invalid (I): the cache index and cache line contents are invalid.
FIG. 1
illustrates a prior art shared memory cache coherent multiprocessor system
100
using snoop-in and snoop-out logic to service snooped requests in accordance with a MOSEI cache coherency protocol. There is shown one or more processor modules or nodes
102
A-
102
N connected to a bus interconnect structure
104
operated in accordance with a snoop protocol. Each node
102
includes a processor
106
, a cache memory
108
, a main memory unit
110
, a bus watcher
112
as well as other components not shown. The main memory unit
110
stores data that is local to the node
102
and data that is shared in one or more of the nodes
102
. This data can also be resident in the cache memory
108
. Each node
102
is associated with a specific address range of the shared memory.
The cache memory
108
is coupled to the main memory unit
110
and the bus watcher
112
. The cache memory
108
attempts to service the memory requests received from the processor
106
from either the cache memory
108
or the main memory unit
110
. In the event the requested data cannot be obtained by the memories associated with the processor, the request is broadcasted on the snoop bus
104
.
The bus watcher
112
is used to monitor the memory requests broadcasted on the snoop bus
104
which pertain to the data resident in the node's cache memory
108
or associated with the node
102
. When a read miss transaction is snooped from the snoop bus
104
, the bus watcher
112
transmits the request to the cache memory
108
. If the requested data item is stored in the cache memory
108
, the state associated with the cache line is returned as will be described below. If the requested data item is associated with the processor's shared memory address range, the data item is fetched from the main memory unit
110
and transmitted to the requesting node
102
.
This particular multiprocessor system
100
uses snoop-in and snoop-out logic to implement the snoop protocol. The snoop-in logic includes a set of shared-in and owned-in signals and associated logic components and the snoop-out logic includes a set of shared-out and owned-out signals and associated logic components. Each processor's cache memory
108
receives a shared_in and owned_in signal and transmits a shared_out and owned_out signal. The shared_out signal is used to indicate whether the data associated with a snooped address is stored by the processor in the shared state (i.e., stored in the ‘E’ or ‘S’ state in accordance with the MOSEI protocol) and when the snooped command is a read miss. The owned_out signal is used by each processor to indicate whether the data associated a snooped address is owned by the processor and may have been modified by the processor (i.e., stored in the ‘M’ or ‘O’ state in accordance with the MOSEI protocol).
The shared_in signal is used to indicate whether the snooped cache line is shared. The processor initiating the snooped request uses this signal to store the requested cache line in either the ‘E’ or ‘S’ state. The cache line is stored in the ‘E’ state when the signal indicates that the cache line is not shared by another processor and the cache line is stored in the ‘S’ state when the signal indicates that the cache line is shared by one or more processors. The owned_in signal is used to indicate that the processor is to provide the requested cache line.
At each snoop cycle, the bus watcher
112
snoops a requested address and command from the bus
104
. The shared_out signals from each processor is set accordingly and transmitted to a first OR logic unit
116
which generates the corresponding shared_in signals, as shown in FIG.
2
A. The owned_out signals from each processor are also set and transmitted to a second OR logic unit
118
which generates the corresponding owned_in signals, as shown in
FIG. 2B. A
processor asserting its shared_out signal provides the requested data and alters the state of the cache line in accordance with the MOSEI protocol. The processor receiving a shared_in signal that is asserted stores the requested data in the corresponding MOSEI state.
At the same time that each processor
106
snoops a requested address and command from the bus
104
, the main memory unit
110
in the processor
106
associated with the address is accessed. In the case of a read miss, the requested data is fetched from the associated main memory unit
110
an
Pennie & Edmonds LLP
Sun Microsystems Inc.
Thai Tuan V.
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