Computer graphics processing and selective visual display system – Computer graphics display memory system – Plural storage devices
Reexamination Certificate
1998-07-01
2001-07-10
Chauhan, Ulka J. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Plural storage devices
C345S503000, C345S533000, C345S557000
Reexamination Certificate
active
06259459
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to image data processing. More particularly, this invention relates to image data processing of pixel data arranged in raster lines and stored within an image frame memory prior to being manipulated by an image processor.
2. Description of the Prior Art
It is known to provide image-processing systems that include an image frame memory for storing raster lines of pixel data. The pixel data is read from the image frame memory one raster line at a time to drive a display device. The image pixel data is also read from the image frame memory by an image processor that performs manipulations, such as filtering operations, upon the pixel data.
It is a constant aim within image data processing systems to increase the speed with which the processing is performing. In addition, it is also highly desirable, particularly in portable and battery powered devices, that the power consumption should be reduced.
SUMMARY OF THE INVENTION
Viewed from one aspect of the present invention provides, an apparatus for processing image data, said apparatus comprising:
(I) an image frame memory for storing pixel data defining an image, said pixel data being divided into raster lines of pixel data values;
(ii) a data buffer memory, coupled to said image frame memory via an image frame memory bus, for storing a subset of said raster lines of pixel data values defining said image;
(iii) an image processor, coupled to said data buffer memory via an image processor bus, for performing image processing upon said subset of said raster lines of pixel data values stored in said data buffer memory; wherein
(iv) said data buffer memory has a plurality of banks of memory cells, each bank of memory cells being divided into a plurality of rows and a plurality of columns of memory cells;
(v) said image processor bus transfers data words between said data buffer memory and said image processor, each data word comprising pixel data values for a plurality of pixels within said image;
(vi) said image processor and said data buffer memory being operable in an intra-raster-line mode to read one bank of memory cells to transfer a data word comprising a plurality of spatially adjacent pixel data values from within one raster line; and
(vii) said image processor and said data buffer memory being operable in an inter-raster-line mode to read a plurality of banks of memory cells to transfer a data word comprising a plurality of pixel data values from within differing raster lines.
The present invention recognizes that the way in which the image frame memory stores raster lines of pixel data, whilst well suited to driving a display device, is not as well suited to providing access to that data by the image processor in an efficient manner. In particular, the image processor will often wish to access the same pixel values in several different orders depending upon the manipulation being performed. For example, a horizontal spatial filtering operation will usually access the pixel values along the direction of the raster lines, whilst a vertical spatial filtering operation will access the pixel data values in a direction perpendicular to the raster lines, whilst temporal filtering will access pixel data values from equivalent raster lines in different frames.
With modem image processors, it is usual for pixel values to be transferred between the memory devices and the processor on a relatively wide bus several pixel values at that time. This is efficient in increasing speed and reducing power consumption. However, unless the pixel values are arranged in a suitable order within the image frame memory, then such multiple pixel data value transfers cannot readily be performed. A standard image frame memory is normally accessed by providing a start address beginning with which a sequence of pixel values along the raster line direction are returned. Accordingly, in the case of a vertical filter operation in which the required pixel data values are not in sequential address order within the frame memory, many more memory accesses have to be performed, or the image processor has to have a large register capacity in order to itself buffer sufficient pixel values to put them into the necessary vertical order.
The present invention addresses this problem by providing a special purpose data buffer memory between the image frame memory and the image processor. This data buffer memory stores a number of raster lines of pixel data (a subset of the raster lines stored by the image frame memory) and allows the image processor to access these in different orders that are better suited to the requirements of the image processor. In particular, the raster data may be written into the banks of memory cells in one order, but read from the data buffer memory in a different order using data words comprising multiple pixel values thus making full use of the available bus bandwidth and reducing the burden upon the image processor to provide reordering or bit slicing functions.
One type of manipulation that often needs to be performed by image processors is horizontal filtering. Accordingly, in the preferred embodiments of the invention, in said intra-raster-line mode, said image processor performs spatial filtering in a direction along said one raster line.
When operating in the inter-raster-line mode, the pixel data values could be taken from memory cells having different relative locations within each bank. However, the control and operation of the data buffer memory are improved in embodiments in which said data word comprises a plurality of pixel data values taken from corresponding row and column positions within each of a plurality of different banks of memory cells.
Whilst the present invention provides advantages for image processors performing many different types of image data manipulation, the advantages are particularly strong and the problem addressed otherwise burdensome in embodiments in which said plurality of banks of memory cells store spatially adjacent raster lines, said data word comprises spatially adjacent pixel data values in a direction perpendicular to said raster lines and said image processor performs spatial filtering in said direction perpendicular to said raster lines.
Another advantageous application of the invention arises in emibodiments in which said plurality of banks of memory cells store temporally adjacent raster lines, said data word comprises temporally adjacent pixel data values from a common spatial position within said image and said image processor performs temporal filtering at said common spatial position.
The present invention may be implemented without requiring excessive modification to existing image processors by providing preferred embodiments in which plurality of banks of memory cells within said data buffer memory form a contiguous address space that is accessed using addresses generated by said image processor.
In this way, the image processor can use its normal ability to generate addresses for memory accesses and have these interpreted by the data buffer memory depending upon the mode in which the system is operating to a return the appropriate pixel data values within the data word. The image processor needs to control the mode, but this may be relatively easily managed using registers storing control flags that are written under program control by the image processor.
Depending upon the size of each pixel data value, the banks of the memory cells may be able to store multiple, one or less than one raster line. Having the data buffer memory store multiple raster lines within one bank is somewhat wasteful as the image frame memory is already storing multiple raster lines within a block. In this circumstances it would be more efficient to consider reducing the data buffer memory size to reduce the circuit area and expense of the system. Accordingly, it is most advantageous to match the pixel value size and data buffer memory capacity such that each bank of memory cells stores either one or a fraction of one raster line. Whe
ARM Limited
Chauhan Ulka J.
Nixon & Vanderhye P.C.
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