Apparatus and method for high speed data transfer

Details Apparatus and method for high speed data transfer Apparatus and method for high speed data transfer

2007-11-27

2007-11-27

Auve, Glenn A. (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S058000, C713S500000

Reexamination Certificate

active

10740948

ABSTRACT:
An improved target and initiator. The initiator provides a starting address and length information on a bus synchronously with a clock signal. While the starting address and length information are present on the bus, the initiator provides a write or a read request signal that is activated and deactivated synchronously. The initiator then receives from the target unit a grant signal that is activated and deactivated synchronously. After the grant signal is deactivated, for a write operation, the initiator provides a number of write data items on the bus synchronously for capture by the target unit. For a read operation, the target provides a number of read data items on the bus synchronously for capture by the initiator unit. One data item provided in each clock cycle of the clock signal and the number of data items is determined by the length information provided.

REFERENCES:
patent: 5463753 (1995-10-01), Fry et al.
patent: 5473762 (1995-12-01), Krein et al.
patent: 6651148 (2003-11-01), Widdup
patent: 6748505 (2004-06-01), Dakhil
patent: 6782460 (2004-08-01), Satagopan et al.
patent: 7155631 (2006-12-01), Kiriake

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