Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1998-07-31
2002-05-21
Vo, Don N. (Department: 2631)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C327S234000, C327S235000, C327S237000
Reexamination Certificate
active
06393083
ABSTRACT:
BACKGROUND
1. Technical Field
The present application relates generally to a digital phase shifter and, more particularly, to an apparatus and method for providing an improved hardware implementation of a digital phase shifter.
2. Description of the Related Art
Modern communications systems often require the implementation of complex digital signal processing algorithms. One such algorithm is used in a conventional digital phase shifter (or mixer). A digital phase shifter is a key functional component in a large number of modern communication systems such as Direct Satellite System (DSS) receivers, digital cellular phones, satellite modems, and wireless local area network (LAN) modems. In particular, one important application of the digital phase shifter is in a digital phase-locked loop (PLL) which is used to remove phase and/or frequency error from a received signal. The use of digital PLLs simplify system design by obviating the need for external analog voltage-controlled oscillators and associated circuitry.
Referring now to
FIG. 1
, a block diagram illustrates a conventional digital communications demodulator having a digital phase shifter. The operation of the conventional digital phase shifter will be described in the context of the digital communications demodulator since this is one of its primary applications. In the system diagram of
FIG. 1
, a radio signal is received by an antenna
10
and then translated from a carrier frequency to baseband (or “zero-IF”) I and Q signals by a quadrature demodulator
12
. The baseband I and Q signals (i.e., complex signals) respectively refer to the “in-phase” and “quadrature phase” components of the radio signal. As shown in
FIG. 2
, the I and Q baseband signals form a complex vector “z” in a cartesian plane, where the tip of the vector “z” is equal to (I+jQ). In addition z, I and Q can be represented as a function of time using the functional notation z(t)=I(t)+jQ(t), where “j” is equal to the square root of negative 1, and represents a location in the Cartesian plane of (0,1).
Referring back to
FIG. 1
, the analog I and Q signals from the quadrature demodulator
12
are digitized by a first analog-to-digital (A/D) converter
14
and a second A/D converter
16
, respectively, and the digitized I and Q signals are sent to a digital demodulator
18
. The digital demodulator
18
includes a digital phase shifter (mixer)
20
which receives the digitized I and Q signals and mixes them with a locally generated phase reference &phgr;(n) so as to apply a phase correction to the digitized samples. The phase is normally updated on a sample-by-sample basis so that the system can remove the phase error effects due to frequency offset or other dynamic phase fluctuations which may occur during transmission in the radio channel. The phase-corrected samples are then integrated by a matched-filter correlator
22
which produces an estimate of the transmitted information symbol. The transmitted information symbol is transformed into information bits (data) by a decoder
24
.
The phase reference &phgr;(n) is typically provided by a carrier recovery module
26
which utilizes an algorithm that is driven by symbol decision-error directed computations provided by the decoder
24
. The carrier recovery module
26
determines the correct phase &phgr;(n) to apply to the digital phase shifter
20
in order to cancel the phase error on the digitized I/Q samples that are received by the digital demodulator
18
. In particular, the digital phase shifter
20
rotates the vector z=I+jQ (which represents corresponding I/Q samples) by the phase reference angle &phgr;(n). Mathematically, the rotation of the complex vector. “z” by phase “&phgr;” is accomplished through multiplication with a complex exponential e
j&phgr;
(i.e., (I+jQ)*e
j&phgr;
).
Typically, conventional digital phase shifters used in high data rate systems such as DSS receivers or high speed wireless LANs are implemented in hardware. The conventional hardware-based digital phase shifter employs a read-only memory. (ROM) lookup table and a complex-multiply operation. Referring now to
FIG. 3
, a block diagram illustrates a conventional hardware realization for a conventional digital phase shifter, such as the one shown in FIG.
1
. In
FIG. 3
, I(n) and Q(n) represent discrete samples which are received by the digital phase shifter
20
, &phgr;(n) represents the correction phase applied to the input I(n) and Q(n) samples, and Iout(n) and Qout(n) represent the phase-corrected samples output from the digital phase shifter
20
. The digital phase shifter
20
includes a complex multiply module
20
b
which multiplies the input samples I(n) and Q(n) (i.e., I(n)+jQ(n)) by the complex exponential e
j&phgr;
. Specifically, since e
j&phgr;
=cos(&phgr;)+jsin(&phgr;) by Euler's identity, the complex multiply module
20
b
performs a fast phase-rotation by first retrieving the values for cos(&phgr;) and sin(&phgr;) from a lookup ROM
20
a
, and then performing one complex multiplication (i.e., [I(n)+jQ(n)]*[cos(&phgr;)+jsin(&phgr;)]) to form the phase-rotated output samples (i.e., Iout(n)=I(n) cos(&phgr;)−Q(n) sin(&phgr;) and Qout(n)=I(n) sin(&phgr;)+Q(n) cos(&phgr;)).
As shown, the complex multiplication requires four multiplications and two additions to generate the phase-corrected output samples. The complex multiplication process of the conventional digital phase shifter
20
requires the implementation of sophisticated digital multipliers. There is a need, therefore, for an improved hardware-based digital phase shifter which utilizess a simplified phase correction process and obviates the need for the complex digital multipliers and ROM of the conventional hardware-based digital phase shifter.
SUMMARY
The present application is directed to an apparatus and method for an improved hardware implementation of a digital phase shifter which provides a simplified process for phase correction of digital signals and eliminates the use of a lookup ROM and complex digital multipliers. The present digital phase shifter operates by applying a phase correction to digital samples in separate phase-shift stages, where each phase-shift stage performs a phase rotation by an amount specified directly by the binary values of an integer input phase.
In one aspect, an apparatus for applying a phase shift to a complex digital signal, comprises: a plurality of phase shift stages each having a phase shift value associated therewith, whereby each of said plurality of phase shift stages selectively applies the corresponding phase shift value to the complex digital signal.
REFERENCES:
patent: 4736328 (1988-04-01), Vatis et al.
patent: 5451894 (1995-09-01), Guo
patent: 5797847 (1998-08-01), Miller et al.
F. Chau & Associates LLP
Vo Don N.
LandOfFree
Apparatus and method for hardware implementation of a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and method for hardware implementation of a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for hardware implementation of a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2896242