Electrical computers and digital data processing systems: input/ – Interrupt processing – Programmable interrupt processing
Reexamination Certificate
1999-08-17
2002-05-28
Shin, Christopher B. (Department: 2182)
Electrical computers and digital data processing systems: input/
Interrupt processing
Programmable interrupt processing
C710S048000, C710S301000, C710S305000, C710S303000, C710S315000
Reexamination Certificate
active
06397284
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to computer systems of the kind that allow peripheral devices to be plugged in and dynamically configured while the computer is running, more especially to the handling of interrupts generated by such peripheral devices.
Current personal computers (PC's) are designed to allow peripheral devices to be connected to the main system hardware.
One kind of bus for connecting peripheral devices is the Industry Standard Architecture (ISA) bus. The ISA bus is an older design of medium speed computer bus which has been in use since the 1980's and is still present on most current IBM compatible personal computers.
Another, more modern, kind of bus is defined by the Personal Computer Memory Card International Association (PCMCIA). Peripheral devices conforming to this standard are sometimes referred to as PCMCIA cards. The PCMCIA standard has been implemented in the form of a medium speed computer bus designed to allow miniature peripheral devices to be plugged into laptop and desktop computers, for example: modems, storage devices etc.
The PCMCIA bus is electrically similar to an ISA bus, but has the additional functionality of allowing dynamic configuration of a PCMCIA card by the PC as it is plugged in. This means that the computer does not have to be turned off to add new hardware in the form of a PCMCIA card. This capability is sometimes referred to using the terms “hot-insertion” and “plug-n-play”. An automatic resource allocation and configuration process is effected by software and is invoked when a new piece of PCMCIA compliant hardware is detected by the PC. This process is designed to simplify hardware installation from the end-user's point of view.
Although PCMCIA cards are in widespread use and offer the advantage of a dynamic insertion capability, a problem arises when external PCMCIA cards are connected to a peripheral component interconnect (PCI) bus of a PC through a PCI-to-PCMCIA bridge, as will be described further below.
A PCI bus is the main system bus in many current PC's. A PCI bus is a high speed bus that can be used to transfer data and commands around the PC motherboard and beyond. The PCI bus standard provides four possible PCI interrupt signals; INTA#, INTB#, INTC# and INTD#, referred to generically as INTX#. A “typical” add-in PCI board will have only one function and will, by convention, only connect to INTA#. INTB# through INTD# are intended for additional optional functions on the same board and are used by so-called multi-function PCI boards. For example, a board that offers three distinct functions would connect INTA# to the first function, INTB# to the second and INTC# to the third.
A bridge is a generic two-port or multi-port device which connects to a PCI bus on one “side” and to another bus, on the other “side”. The other bus can itself be a PCI bus, but equally it can be of any other type, for example a PCMCIA bus. A bridge serves to expand or extend the PCI bus system without violating the fundamental electrical parameters that define the PCI bus.
One function performed by a PCI-to-PCMCIA bridge is to map an input interrupt signal to one of sixteen outputs, corresponding to the legacy interrupt channels (LICs) which formed part of the ISA bus and that are implemented in current IBM compatible PC's. Interrupt mapping is the logical connection of an interrupt signal to one of the system's available LICs. The association is made by configuration of the bridge's hardware to direct the interrupt signal to the required LIC hardware line. The LICs are named IRQ
0
to IRQ
15
inclusive and originated from early IBM compatible PC's that used 8259 type interrupt controller chips. It is noted that due to the one-to-one correspondence between LICs and the interrupts used as part of the ISA bus, LICs are often referred to as “ISA interrupts”. The LICs are distributed out among the system's internal and external peripheral devices, usually with each device being mapped to one LIC.
Each PCMCIA device can use a single interrupt and that interrupt is dynamically allocated to the PCMCIA device on installation by the operating system. The mapping is used to configure the bridge hardware and is also stored in the operating system's own internal configuration tables. Subsequently, the application software can obtain the LIC mapping from the operating system to determine the LIC that the PCMCIA card has been mapped to. The application software is thus able to register itself as an interrupt handler for the relevant LIC. The interrupt allocation is performed dynamically based on which LICs are currently free and what resource requirements other devices in the system may have. It is important to emphasize that the mapping is not fixed. It can change freely. For example, the operating system may allocate the same PCMCIA card LIC channel IRQ
12
on one day and IRQ
11
on the next day.
For a PCI-to-PCI bridge, all relevant interrupt signals are passed through the bridge. However, for a PCI-to-PCMCIA bridge connected via a PCI expansion connector, this is not the case. As a result software failure can occur when PCMCIA cards are plugged into an adapter device that uses a PCI-to-PCMCIA bridge connected to a PCI expansion connector. This situation is now described with reference to
FIG. 1
of the accompanying drawings.
FIG. 1
shows a PCMCIA card
10
that is connected, or plugged into, a PCI-to-PCMCIA bridge
20
that is in turn connected to, or plugged into, a PCI expansion connector
30
of a PC by a corresponding bridge PCI expansion connector
29
that includes pins for the PCI bus data, and address and control lines
40
, and the PCI interrupt lines
25
to
28
. Certain internal components of the PC that are relevant to interfacing with the PCI expansion connector
30
are also shown, these components being labeled with reference numerals in the range
40
to
60
.
The PC components illustrated are the PCI interrupt channel connections INTX#
41
to
44
, and the PCI bus
40
. The PCI bus
40
is connected to the main system PCI bus of the PC. The PCI interrupt channel connections
41
to
44
connect to respective demultiplexers
56
to
59
which serve to map the respective four PCI interrupts to their allocated LIC
60
for conveying IRQ
0
. . .
15
between a programmable interrupt controller (PIC)
50
and the PC's peripheral devices, of which the illustrated PCI expansion connector
30
is but one. The demultiplexers
56
to
59
are components of system board PCI interrupt mapping circuitry
55
.
The sixteen LICs
60
are connected to the programmable interrupt controller (PIC)
50
. A PIC is a device that prioritizes and multiplexes the 16 LICs and sends an interrupt request to the processor for each LIC that is in an active state. Typical IBM compatible computers use two Intel 8259 PICs (or compatible) in cascade. Moreover, it is noted that the PCI interrupts once mapped to LICs are handled slightly differently from ISA-type interrupts since the PCI interrupts are level sensitive whereas the ISA-type interrupts are edge sensitive.
An interrupt sent to the processor by the PIC
50
constitutes an interrupt request to alert the processor that a device requires servicing by software. The interrupt is sent (or asserted) to the PIC using either an INTX# signal, or on the LIC interconnects
60
using an IRQ
0
. . .
15
, and then from the PIC to the processor on a dedicated processor signal line (not shown) using an INTX# signal, or on the LIC interconnects
60
using an IRQ
0
. . .
15
signal. The interrupt request is then handled by the processor calling an appropriate interrupt servicing routine (ISR) in system software.
The PCMCIA card
10
has an interface including a single interrupt
12
. In order for the interrupt
12
to be usable by the PC, the interrupt
12
is mapped to one of the LICs of the PC. This mapping process is done by a routing circuit in the form of a demultiplexer
24
cont
Prescott Richard B
Sleeman Peter T
Conley & Rose & Tayon P.C.
Elan Digital Systems Limited
Meyertons Eric B.
Shin Christopher B.
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