Apparatus and method for handling multiple mergeable misses in a

Details Apparatus and method for handling multiple mergeable misses in a Apparatus and method for handling multiple mergeable misses in a

1998-01-21

2000-11-07

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711119, 711144, G06F 1208

Patent

active

061450545

ABSTRACT:
A method and apparatus for merging multiple misses to a multi-level cache is provided to improve the performance of the cache. A first and second non-blocking cache are each provided with miss queues storing entries corresponding to access requests not serviced by the respective caches. The first and second miss queues have an indicator associable with each of said entries in the respective miss queues indicating that the entry is a primary reference to data located at the address associated with said entry. If a subsequent instruction generates a cache miss accessing data associated with an entry in a miss queue, the subsequent miss is merged with the appropriate entry in the miss queue and serviced when the primary reference is serviced.

REFERENCES:
patent: 5809530 (1998-09-01), Samra et al.
patent: 5832297 (1998-11-01), Ramagopal et al.

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