Electrical computers and digital processing systems: processing – Processing control – Branching
Reexamination Certificate
2007-04-10
2007-04-10
Chan, Eddie (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Branching
C712S204000
Reexamination Certificate
active
09906381
ABSTRACT:
A branch control apparatus in a microprocessor. The apparatus includes a branch target address cache (BTAC) that caches indications of whether a branch instruction wraps across two cache lines. When an instruction cache fetch address of a first cache line containing the first part of the branch instruction hits in the BTAC, the BTAC outputs a target address of the branch instruction and indicates the wrap condition. The target address is stored in a register. The next sequential fetch address selects a second cache line containing the second part of the branch instruction. After the two cache lines containing the branch instruction are fetched, the target address from the register is provided to the instruction cache in order to fetch a third cache line containing a target instruction of the branch. The three cache lines are stored in order in an instruction buffer for decoding.
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Bean Brent
Henry G. Glenn
McDonald Thomas C.
Chan Eddie
Davis E. Alan
Huffman James W.
IP-First LLC
Li Aimee J.
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