Apparatus and method for generating distributed traffic

Details Apparatus and method for generating distributed traffic Apparatus and method for generating distributed traffic

2005-06-07

2005-06-07

Ray, Gopal C. (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S100000, C370S257000, C709S253000

Reexamination Certificate

active

06904487

ABSTRACT:
An apparatus and method for generating distributed traffic in nodes coupled to a bus, wherein one node reads information on other nodes and generates traffic, includes a bus interface unit and a control unit receiving signals. The signals are transmitted from the nodes via the bus interface unit, to detect a bus reset and determine the number N of nodes coupled to the bus and a node ID number K of a node having the control unit. The information on the nodes is read in a predetermined order, starting from a reference node with node ID number K+M, wherein M is an integer larger than 1−K and smaller than N−K. The apparatus controls the order of generation of read transactions in each node for reading information from the other nodes coupled to a bus. The traffic load applied to each node is distributed to reduce an initial bus stabilization time.

REFERENCES:
patent: 6512767 (2003-01-01), Takeda et al.
patent: 6735619 (2004-05-01), Sawada
patent: 6754184 (2004-06-01), Miyano et al.
patent: 6816967 (2004-11-01), Iijima et al.
patent: 10-290237 (1998-10-01), None
patent: 10-2001-0018994 (2001-03-01), None
“Testing CPU based boards for functionality using bus cycle signature system” by Sabapathi, S.R. (abstract only) Publication Date: Dec. 2-4, 1998 Singapore.

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