Apparatus and method for generating a stride used to derive a pr

Details Apparatus and method for generating a stride used to derive a pr Apparatus and method for generating a stride used to derive a pr

1997-06-25

2000-10-24

Nguyen, Hiep T.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711213, 711220, 711131, 712207, G06F 1208

Patent

active

061382124

ABSTRACT:
A central processing unit (CPU) of a computer has a data caching unit which includes a novel dual-ported prefetch cache configured in parallel with a conventional single-ported data cache. If a data cache miss occurs, the requested data is loaded into the data cache and into the prefetch cache. Thereafter, each data request which results in a prefetch cache hit triggers the prefetching of data into the prefetch cache. A data load history tracking circuit maintains a running history of instructions that request data from external memory, and uses the resulting loop heuristics of these instructions to generate a stride. The stride is used to derive a prefetch address which identifies data that is predicted to be soon requested in subsequent instructions. Data corresponding to the prefetch address is then loaded into the prefetch cache. Thus, where a subsequent instruction requests data which has been prefetched into the prefetch cache, latencies associated with external memory may be hidden, thereby increasing the data bandwidth of the CPU.

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