Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-06-25
2000-08-01
Nguyen, Hiep T.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711213, 711118, 711120, 711122, 711125, 712207, G06F 1200
Patent
active
060981547
ABSTRACT:
A central processing unit (CPU) of a computer has a data caching unit which includes a novel dual-ported prefetch cache configured in parallel with a conventional single-ported data cache. In response to a data cache miss, the requested data is fetched from external memory and loaded into the data cache and into the prefetch cache. Thereafter, if a prefetch cache hit occurs, the physical address of the corresponding data request is provided to a prefetch engine which, in turn, adds a stride to the physical address to derive a prefetch address. This prefetch address identifies data which is predicted to be soon requested in subsequent instructions of the computer program. Data corresponding to the prefetch address is then retrieved from external memory and loaded into the prefetch cache. This prefetching operation frequently results in the prefetch cache storing data that is requested by subsequently executed instructions in a computer program. When this condition occurs, data is immediately retrieved from the prefetch cache and provided to execution units within the CPU, thereby eliminating latencies associated with external memory.
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Chiacchia Denise
Lauterbach Gary
Lopez-Aguado Herbert
Galliani William S.
Nguyen Hiep T.
Sun Microsystems Inc.
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