Apparatus and method for fractional frequency division using...

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

Reexamination Certificate

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Details

C375S373000, C327S156000, C331S002000

Reexamination Certificate

active

07356111

ABSTRACT:
A phase-locked loop (PLL) frequency synthesizer capable of being tuned in small step sizes. The PLL frequency synthesizer includes a PLL circuit. A phase-locked loop (PLL) frequency synthesizer includes a PLL core and a feedback frequency divider. The PLL core receives an F(in) signal and generates a plurality of multiphase output signals having an F2 frequency, where F2=(in)(P+Δp). The feedback frequency divider receives the plurality of multiphase output signals and generates a feedback signal having a frequency of F2/(P+Δp), where P is an integer and Δp is a fractional value less than one.

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