Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-02-14
2002-03-19
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S311000, C257S296000, C257S510000, C438S387000, C438S391000
Reexamination Certificate
active
06359299
ABSTRACT:
BACKGROUND
1. Technical Field
This disclosure relates to semiconductor devices and more particularly, to an apparatus and method for forming deep trench isolation layers for semiconductor memories.
2. Description of the Related Art
Semiconductor memories such as dynamic random access memories (DRAM) typically include memory cells. These memory cells include storage nodes. Generally these storage nodes are formed within deep trenches etched into substrates of the semiconductor memory chip. The storage nodes are accessed using an access transistor which allows charge to be stored in the storage node or retrieves charge from the storage depending on whether the desired action is a read or write function. It is often necessary to ensure that the storage node is sufficiently electrically isolated from a gate conductor.
One way to ensure sufficient electrical isolation of the storage node is to provide a top trench oxide layer over the storage node. The storage nodes typically include polysilicon material that partially fills the deep trench. During fabrication the polysilicon leaves a recess remaining at the top of the trench. An oxide (silicon dioxide) is deposited over the surface of the semiconductor device. During the oxide deposition, oxide is formed over the polysilicon in the trench. Other portions of the deposited oxide are removed by planarizing the surface of the semiconductor device and by recessing the oxide to leave a 30-50 nm oxide layer at the bottom of the recess. This oxide layer is referred to as a trench top oxide or isolation.
The oxide recessing is difficult to control. This difficulty introduces a lot of variability in the remaining oxide layer thickness. The trench top oxide thickness is an important parameter and must be maintained in order for the semiconductor memory to work properly. As described above, the trench top oxide electrically isolates the storage node from the gate conductor of the semiconductor device.
Therefore, a need exists for a trench top dielectric having a controlled thickness. A further need exists for a method of providing the trench top isolation for transistors formed on top of deep trenches.
SUMMARY OF THE INVENTION
A method for controlling isolation layer thickness in deep trenches for semiconductor memories in accordance with the present invention includes the steps of providing a deep trench having a storage node formed therein, the storage node having a buried strap, depositing an isolation layer on the buried strap for providing electrical isolation for the storage node, forming a masking layer on the isolation layer to mask a portion of the isolation layer in contact with the buried strap and removing the isolation layer except the portion masked by the mask layer such that control of a thickness of the isolation layer is improved.
In other useful methods in accordance with the present invention, the step of depositing the isolation layer may include depositing the isolation layer by chemical vapor deposition or by plasma enhanced chemical vapor deposition. The isolation layer may include an oxide, a nitride or a combination of both. The thickness of the isolation layer is preferably between about 20 nm to about 50 nm. The step of forming the masking layer may include the step of depositing a material which is selectively etchable relative to the isolation layer. The material may include polysilicon.
A method for fabricating a memory cell having trench isolation includes the steps of providing a deep trench having a storage node formed therein, the storage node having a buried strap, depositing an isolation layer on the buried strap for providing electrical isolation for the storage node, forming a masking layer on the isolation layer to mask a portion of the isolation layer in contact with the buried strap, selectively etching the isolation layer relative to the masking layer to leave the portion masked by the masking layer, opening up an isolation trench in communication with the deep trench by removing at least a portion of the substrate adjacent to the deep trench, filling the isolation trench with a dielectric material to provide trench isolation.
In other particularly useful methods, the step of forming an access device for accessing the storage node disposed within the trench below the isolation layer is preferably included. The step of forming an access device may include forming a transistor having a channel formed in the substrate for electrically coupling the buried strap to a bitline. The step of recessing the portion of the substrate adjacent to the deep trench such that the transistor is formed a greater distance away from the deep trench is preferably included. The step of forming a transistor gate adjacent to the trench isolation and adjacent to the isolation layer in a top portion of the deep trench may also be included. The isolation layer may be deposited by chemical vapor deposition. The isolation layer may include an oxide a nitride or a combination of both. The thickness of the isolation layer is preferably between about 20 nm to about 50 nm. The masking layer may include polysilicon. The trench isolation may include shallow trench isolation or raised shallow trench isolation.
A method for fabricating a vertical transistor includes the steps of providing a substrate having trenches formed therein, each trench having a storage node formed therein, the storage node having a buried strap, forming an isolation layer on the buried strap, laterally etching the substrate to recess a step into the substrate such that the recess extends beyond sides of the trench, the recess being in communication with the trench and forming a gate conductor in the recess such that a channel is formed adjacent to the gate conductor for providing electrical conduction between the buried strap and a conductive line upon activation of the gate conductor.
In other methods of fabricating a vertical transistor, the step of laterally etching preferably includes laterally etching by a dry etch process, such as a chemical downstream etch or a reactive ion etch process. The conductive line may include a bitline.
A semiconductor memory includes a substrate having a plurality of deep trenches formed therein. Each deep trench has a buried strap formed therein for accessing a storage node disposed within the deep trench, a deposited isolation layer formed on the buried strap for providing electrical isolation for the buried strap and a masking layer formed on the isolation layer for providing a mask for a portion of the isolation layer in contact with the buried strap, the masking layer being selectively etchable relative to the isolation layer wherein the masking layer provides improved control of a thickness of the isolation layer.
In alternate embodiments of the semiconductor memory, the masking layer may include polysilicon. The isolation layer may include an oxide, a nitride or a combination of both. The thickness of the isolation layer is preferably between about 20 nm to about 50 nm. An access transistor may be included having a gate formed in the trench and having at least a portion of the gate in contact with the isolation layer, the transistor having a channel formed in the substrate adjacent to the gate for electrically coupling the buried strap to a bitline. The trench isolation may be formed in at least a portion of the trench for isolating the gate from the storage node. The substrate may include a recessed portion, the recessed portion for enabling the gate and channel to be located further away from the trench.
A method for fabricating a vertical transistor for semiconductor memories with deep trenches includes the steps of providing a substrate having deep trenches formed therein, each deep trench having a storage node formed therein, the storage node having a buried strap recessed below a top surface of the substrate, forming an isolation layer on the buried strap and on trench sidewalls, depositing a dummy layer on the isolation layer, opening up an isolation trench in communication with the deep trench by removing at least
Infineon - Technologies AG
Lee Eddie
Lee Eugene
LandOfFree
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