Electrical computers and digital processing systems: processing – Processing control – Branching
Reexamination Certificate
2008-05-13
2008-05-13
Chan, Eddie (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Branching
C708S498000, C708S495000, C712S222000
Reexamination Certificate
active
10880713
ABSTRACT:
An apparatus and method for floating point exception prediction and recovery. In one embodiment, a processor may include instruction fetch logic configured to issue a first instruction from one of a plurality of threads and to successively issue a second instruction from another one of the plurality of threads. The processor may also include floating-point arithmetic logic configured to execute a floating-point instruction issued by the instruction fetch logic from a given one of the plurality of threads, and further configured to determine whether the floating-point instruction generates an exception, and may further include exception prediction logic configured to predict whether the floating-point instruction will generate the exception, where the prediction occurs before the floating-point arithmetic logic determines whether the floating-point instruction generates the exception.
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Brooks Jeffrey S.
Jordan Paul J.
Sugumar Rabin A.
Alrobaye Idriss
Chan Eddie
Kowert Robert C.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Petro Anthony M.
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