Apparatus and method for fault tolerant operation of a multiproc

Details Apparatus and method for fault tolerant operation of a multiproc Apparatus and method for fault tolerant operation of a multiproc

1993-04-02

1999-07-06

Beausoliel, Jr., Robert W.

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

G06F 1300

Patent

active

059192666

ABSTRACT:
A fault tolerant multiple processor data processing system is described. The system includes a number of processors linked together in a network. One processor is designated the master processor and coordinates the operation of all of the processors. The network is coupled to a number of memory devices which store information which is utilized by the processors. The apparatus includes a redundant mechanism for identifying a failure of a processor. If the master processor fails, a new master processor is selected, in a dynamic manner, from the remaining operative processors. The selection of a new master processor is based upon a contention operation in which the operative processors contend to become the new master processor.

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