Electrical computers and digital processing systems: memory – Address formation – Generating a particular pattern/sequence of addresses
Reexamination Certificate
2005-10-18
2005-10-18
Moazzami, Nasser (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Generating a particular pattern/sequence of addresses
C711S118000, C711S137000
Reexamination Certificate
active
06957317
ABSTRACT:
An apparatus and method facilitating memory data access with generic read/write patterns are described. In one embodiment, the method includes the detection, in response to a load instruction, of a cache hit/cache miss of data requested by the load instruction within a re-tiling (RT) cache. When a cache miss is detected, a block of data is loaded into the RT cache according to the load instruction. This block of data will contain the data requested by the load instruction. Once loaded, a non-horizontally sequential access of the data requested by the load instruction is performed from the RT cache. Finally, the data accessed from the RT cache may be stored into a destination data storage device according to the load instruction.
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Chen Yen-Kuang
Debes Eric
Holliman Matthew J.
Yeung Minerva M.
Blakely Sokoloff Taylor and Zafman
Intel Corporation
Moazzami Nasser
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