Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
1996-12-02
2001-04-17
Teska, Kevin J. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C703S020000, C716S030000
Reexamination Certificate
active
06219630
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a circuit extracting apparatus and a circuit extracting method for extracting circuit information from a mask layout, which are for use in the design of a semiconductor integrated circuit.
With recent advances in processing and designing technology, LSIs (Large-Scale Integrated Circuits) represented by a microprocessor have been increasing rapidly in performance and integration. To implement the LSIs with higher performance and higher integration, it is required to perform circuit design with higher accuracy so that CAD (Computer Aided Design) tools have been playing an important role in high-accuracy circuit design.
The CAD tools closely related to the design accuracy includes a circuit simulator for simulating a designed LSI as an actual device (LSI manufactured in practice) based on a netlist containing information on such elements as a MOS transistor, a capacitor, a resistor, and an inductor and their interconnections as well as characteristic information including the transistor size (transistor width, transistor length), a capacitance value, a resistance value, and an inductance value. The netlist can be extracted from, e.g., the mask layout of the designed LSI by means of a circuit extracting apparatus.
By way of example, a description will be given to conventional LSI simulation using a circuit extracting apparatus and a circuit simulator and performed with respect to the MOS transistor shown in FIG.
14
.
FIG. 14
shows an example of the mask layout of the MOS transistor. As shown in the drawing, the MOS transistor
90
comprises four terminals which are: a gate
91
; a source
92
; a drain
93
; and a substrate
94
. Contacts
95
and
96
provide connections to the source
92
and the drain
93
. The MOS transistor
90
has a transistor width (gate width) W and a transistor length (gate length) L.
Initially, the circuit extracting apparatus extracts a netlist as shown in
FIG. 15
from the mask layout shown in FIG.
14
. The netlist shown in
FIG. 15
describes the MOS transistor
90
and contains data on the transistor size (transistor width W, transistor length L).
Next, the circuit simulator performs circuit simulation based on the netlist shown in FIG.
15
. The circuit simulator determines the drain current and gate capacitance of the MOS transistor
90
shown in
FIG. 14
based on the transistor-size data contained in the netlist shown in FIG.
15
and reproduces the operation of the actual device.
However, the conventional LSI simulation has the following problems.
The conventional circuit extracting apparatus cannot extract a netlist from the mask layout such that the drain current and gate capacitance of the MOS transistor are reproduced with high fidelity in the circuit simulation performed by the circuit simulator.
In real physical devices, the drain currents and gate capacitances of MOS transistors are not necessarily equal if the configurations of the transistor portions (gates) thereof are different even though they have an equal transistor size (transistor width, transistor length). In a typical circuit simulator, however, MOS transistors having an equal transistor size (transistor width, transistor length) are considered to have an equal drain current and an equal gate capacitance.
FIG. 16
shows another example of the mask layout of the MOS transistor, depicting a MOS transistor
90
A with the transistor portion (gate)
91
in a bent configuration. It is assumed here that the MOS transistor
90
shown in FIG.
14
and the MOS transistor
90
A shown in
FIG. 16
have an equal transistor width W and an equal transistor length L. In this case, however, the circuit simulator considers the MOS transistor
90
and the MOS transistor
90
A to have an equal drain current and an equal gate capacitance, though the MOS transistors
90
and
90
A in actual devices have different drain currents and different gate capacitances due to different configurations of the transistor portions
91
.
If the transistor size of the MOS transistor is corrected in the netlist to increase the accuracy of the drain current in circuit simulation, the accuracy of the gate capacitance is reduced. Conversely, if the transistor size is corrected to increase the accuracy of the gate capacitance, the accuracy of the drain current is reduced.
Accordingly, a netlist which allows the drain current and gate capacitance in an actual device to be reproduced with high fidelity in circuit simulation has not conventionally been generated, with the result that circuit simulation has not conventionally been performed with high fidelity.
SUMMARY OF THE INVENTION
To overcome the foregoing problems, the present invention provides a circuit extracting apparatus and a circuit extracting method for extracting circuit information for use in circuit simulation from the mask layout of a semiconductor circuit, thereby achieving high-fidelity reproduction of the drain current and gate capacitance of a transistor in the circuit simulation.
Specifically, the present invention is for obtaining an equivalent transistor size for a transistor contained in the semiconductor circuit based on a configuration of the transistor recognized in the mask layout, such that a drain current of the transistor in the circuit simulation coincides with a drain current of the transistor in an actual device, and virtually generating a corrective capacitance having a capacitance value corresponding to the difference between a gate capacitance of the transistor in the circuit simulation using the equivalent transistor size and a gate capacitance of the transistor in the actual device.
According to the present invention, the difference between the drain current in the circuit simulation and the drain current in the actual device (semiconductor device manufactured in practice) resulting from different configurations of transistor portions can be eliminated by obtaining the equivalent transistor size. On the other hand, the difference between the gate capacitance in the circuit simulation and the gate capacitance in the actual device resulting from high-fidelity reproduction of the drain current by using the equivalent transistor size in addition to the different configurations of the transistor portions can be eliminated by virtually generating the corrective capacitance. Thus, by using the data on the equivalent transistor size and corrective capacitance as the circuit information for use in the circuit simulation, the drain current and gate capacitance of a transistor can be reproduced with high fidelity in the circuit simulation.
The present invention also provides a netlist containing the circuit information extracted by the foregoing circuit extracting apparatus and circuit extracting method.
Alternatively, the circuit extracting apparatus and method according to the present invention is for obtaining an equivalent transistor size for a transistor contained in the semiconductor circuit based on a configuration of the transistor recognized in the mask layout, such that a gate capacitance of the transistor in the circuit simulation coincides with a gate capacitance of the transistor in an actual device, and virtually generating a corrective current source having a current value corresponding to the difference between a drain current of the transistor in the circuit simulation using the equivalent transistor size and a drain current of the transistor in the actual device.
According to the present invention, the difference between the gate capacitance in the circuit simulation and the gate capacitance in the actual device which results from different configurations of the transistor portions can be eliminated by obtaining the equivalent transistor size. On the other hand, the difference between the drain current in the circuit simulation and the drain current in the actual device which results from high-fidelity reproduction of the gate capacitance by using the equivalent transistor size in addition to different configurations of the transistor portions can be eliminated b
Ishikura Satoshi
Umeda Takuya
Yonezawa Hirokazu
Matsushita Electronics Corporation
McDermott & Will & Emery
Phan Thai
Teska Kevin J.
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