Apparatus and method for error free loading of a programmable no

Details Apparatus and method for error free loading of a programmable no Apparatus and method for error free loading of a programmable no

1997-07-23

1999-07-20

Chung, Phung M.

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

714712, 714752, G06F 1134

Patent

active

059251409

ABSTRACT:
An apparatus and method for error free loading of a programmable non-volatile memory device over a serial or parallel data link. The apparatus comprises a host system connected to a unit to be programmed via a data communications link. The host system comprises a central processing unit (CPU) coupled to random access memory (RAM) via a bus, and the unit to be programmed represents a device in which a programmable non-volatile memory is installed. The data to be stored in the programmable non-volatile memory is sent by the host system in data packets to allow error checking to be applied to each block transmitted across the data communications link to the unit to be programmed. The host system builds data blocks in frames, computes an error detection code, and sends the frames containing the data and the error detection code across the data link to the unit to be programmed. The unit to be programmed uses the error detection code to determine if the transmission was successful. If the transfer was error free, the data is loaded into the programmable non-volatile memory in the unit to be programmed. If the frame was received in error, the unit to be programmed sends a frame back to the host system notifying it that the transmission contained an error. This process of sending and acknowledging frames continues until the programmable non-volatile memory in the unit to be programmed is completely programmed.

REFERENCES:
patent: 4754482 (1988-06-01), Weiss
patent: 4831624 (1989-05-01), McLaughlin et al.

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