Static information storage and retrieval – Read/write circuit – Erase
Patent
1993-06-01
1994-10-18
LaRoche, Eugene R.
Static information storage and retrieval
Read/write circuit
Erase
365185, 365900, G11C 1134
Patent
active
053574761
ABSTRACT:
A flash EEPROM array (22) is erased and a threshold voltage distribution of the erased flash EEPROM cells (36, 39-46) is converged to within a predetermined voltage range by using a two-step erasing procedure. In the first step, flash EEPROM array (22) is electrically bulk erased using a conventional bulk erase procedure. Electrons are tunneled from the floating gate (38) to the source, causing cells (36, 39-46) to have a relatively low threshold voltage. In the second step, the threshold voltage distribution of the array (22) is converged to within the predetermined voltage range by grounding the source and drain of each cell (36, 39-46), while concurrently applying a high positive voltage to the control gate (27) of each cell (36, 39-46). Some electrons are tunneled back to the floating gate (38), thus converging the threshold voltage distribution to within a predetermined range.
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Chang Ko-Min
Choe Henry Y.
Kuo Clinton C. K.
Hill Daniel D.
LaRoche Eugene R.
Motorola Inc.
Nguyen Tan
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