Apparatus and method for entering and exiting low power mode

Details Apparatus and method for entering and exiting low power mode Apparatus and method for entering and exiting low power mode

2008-01-29

2008-01-29

Lane, Jack (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S106000, C711S165000, C713S320000, C713S323000, C713S330000

Reexamination Certificate

active

11264301

ABSTRACT:
An apparatus for entering and exiting low power mode comprising a processor having a cache; a power management mechanism connected to said processor for controlling a plurality of power management states, at least one of said power management states being a low latency low power state; a memory subsystem including a self sustaining mechanism connected to said processor for retaining data during said low power state; a pre-fetching routine in said memory subsystem for loading instructions into a cache prior to entering said low power state; a disabling mechanism in said processor for disabling any interrupts that may disturb said pre-fetched instructions; an enabling routine in said memory subsystem for initiating the self sustaining operation of said memory subsystem; a detecting routine connected to said processor for sensing a trigger to exit from said low power state; and a restoring routine in said power management mechanism for restoring the clock of said apparatus; thereby said processor disabling said self sustaining operation and resuming normal operation at the end of said low power state.

REFERENCES:
patent: 5931951 (1999-08-01), Ando
patent: 6122748 (2000-09-01), Hobson
patent: 6571333 (2003-05-01), Jain et al.

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