Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-10-21
1998-09-01
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711133, G06F 1212
Patent
active
058025715
ABSTRACT:
An age-based arbitration scheme for enforcing data coherency in an information handling system is disclosed. As loads and stores access a cache, if a cache miss occurs, a miss request is generated and tagged with the cycle or age in which the miss is detected. If a castout is required, it is also tagged with the cycle in which the load or store access occurred, and the line being replaced or cast out is marked as being invalid in that level of hierarchy. The arbitration rules for the next level of memory hierarchy are defined such that all requests that are generated during a particular cycle are given priority over all of the requests generated during any subsequent cycle. As a result, if a load miss occurs for a cache line which is present in the castout buffer, the castout request tagged with an earlier age will be arbitrated into the next memory hierarchy level prior to the arrival of the newly generated miss requests. The age-based arbitration scheme can also be used for multiple cache accesses occurring in parallel.
REFERENCES:
patent: 5432918 (1995-07-01), Stamm
patent: 5455924 (1995-10-01), Shenoy et al.
patent: 5692152 (1997-11-01), Cohen et al.
Konigsburg Brian R.
Muhich John Stephen
White Steven Wayne
Chan Eddie P.
Ellis Kevin L.
England Anthony V. S.
Galasso Raymond M.
International Business Machines - Corporation
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