Apparatus and method for end of interrupt handling

Details Apparatus and method for end of interrupt handling Apparatus and method for end of interrupt handling

1999-12-30

2004-06-22

Ray, Gopal C. (Department: 2111)

Electrical computers and digital data processing systems: input/

Interrupt processing

C710S269000

Reexamination Certificate

active

06754754

ABSTRACT:

BACKGROUND
1. Field
This disclosure relates to interrupt control and, more particularly, to handling indications of end of interrupts.
2. Background Information
The use of interrupts in computing and electronic systems is common for servicing components of the system. Typically, an interrupt controller receives interrupt requests and generates interrupt vectors in response to these requests. An interrupt service routine (ISR) may be executed in response to such an interrupt request. Typically, an end of interrupt (EOI) vector may then indicate completion of an ISR. Processing EOI vectors has historically not been substantially limiting to system performance. However, improvements in computing efficiency, such as bus frequency increases and microprocessor advancements, increase the likelihood that EOI vector processing times might impact system performance. Therefore, a need exists to reduce the overall time for processing EOI vectors.


REFERENCES:
patent: 5727217 (1998-03-01), Young
patent: 5918057 (1999-06-01), Chou et al.
patent: 6192442 (2001-02-01), Haren et al.
“Out-of-order vector architectures” by R. Espasa, M. Valero and J.E. Smith (abstract only).*
Intel 82093AA I/O Advanced Programmable Interrupt Controller (IOAPIC) Specification, 20 pages.

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