Chemistry: electrical and wave energy – Apparatus – Electrolytic
Reexamination Certificate
2001-10-16
2004-10-12
Valentine, Donald R. (Department: 1742)
Chemistry: electrical and wave energy
Apparatus
Electrolytic
C204S289000, C204S297030, C204S275100, C204S212000
Reexamination Certificate
active
06802947
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to an electroplating apparatus and method using backside electrical contacts.
2. Description of the Related Art
The production of sub-micron sized semiconductor features is a key technology for the next generation of very large scale integration (VLSI) and ultra large scale integration (ULSI) semiconductor devices. However, next generation ULSI and VLSI devices will require a substantial decrease in the interconnect dimensions, which imposes substantial additional manufacturing demands. Further, the multilevel interconnects that lie at the heart of these technologies requires precise processing of high aspect ratio features, such as vias and other interconnects. Reliable formation of these multilevel vias and interconnects is important to the success of VLSI and ULSI devices, and to the continued effort to increase circuit density and quality of individual substrates.
As circuit densities increase, the widths of vias, contacts, and other features, as well as the dielectric materials between them, decreases to sub-micron dimensions, while the thickness of the respective dielectric layers generally remains constant. This results in the aspect ratios for the features, i.e., the feature height divided by width, increasing substantially. Traditional deposition processes, such as chemical vapor deposition (CVD) and physical vapor deposition (PVD), for example, generally have difficulty filling sub-micron sized structures where the aspect ratio of the structure exceeds 2:1, and particularly when the aspect ratio exceeds 4:1. Conventional methods are known to leave voids in sub-micron features that render the feature inefficient or inoperable. Therefore, there is a substantial amount of ongoing effort being directed toward discovering alternative methods for forming substantially void-free sub-micron features having high aspect ratios.
Additionally, traditional systems have used aluminum and its alloys to form interconnects. However, currently, copper and its alloys have become the metals of choice for sub-micron interconnect technology, as copper is known to have a lower resistivity than aluminum, (1.7 &mgr;&OHgr;-cm compared to 3.1 &mgr;&OHgr;-cm for aluminum), a higher current density, and significantly higher electromigration resistance. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed. Further, copper has a good thermal conductivity, is readily available in a highly pure state, and offers excellent adhesion characteristics to silicon.
Although copper is a desirable metal for semiconductor devices, the fabrication choices for depositing copper into very high aspect ratio features, such as 4:1 or greater having 0.351 &mgr; (or less) wide vias, are limited, as CVD and PVD are generally not viable deposition options. As a result of these process limitations, electroplating techniques, which have previously been limited to the fabrication of larger a lines and other features on circuit boards, are now being investigated as a possible method for efficiently and effectively filling sub-micron sized features on semiconductor devices.
Electroplating processes for semiconductor devices typically require a thin, continuous, electrically conductive seed layer to be deposited on the substrate. Electroplating a desired metal is then generally accomplished by applying an electrical bias to the seed layer and exposing the substrate to an electrolytic solution containing metal ions that will plate over the seed layer in the presence of the electrical bias. The seed layer generally is formed of a conductive metal, such as copper, for example, and is conventionally deposited on the substrate using PVD or CVD techniques.
FIG. 1
is a cross sectional view of a conventional fountain plater
100
. Generally, the fountain plater
100
includes an electrolyte container
112
having a top opening, a substrate holder
114
disposed above the electrolyte container
112
, an anode
116
disposed at a bottom portion of the electrolyte container
112
, and a contact ring
120
contacting the production surface of a substrate
122
in order to provide an electroplating bias voltage to the seed layer on the substrate. A plurality of grooves
124
are formed in the lower surface of the substrate holder
114
, and a vacuum pump (not shown) is generally coupled to substrate holder
114
and communicates with the grooves
124
to create a vacuum condition capable of securing the substrate
122
to the substrate holder
114
during processing. Contact ring
120
generally includes a plurality of metallic or semi-metallic contact pins
126
distributed about the peripheral portion of the substrate
122
to define a central substrate plating surface. The plurality of contact pins
126
generally extend radially inwardly over a portion of the perimeter of the substrate
122
and contact the conductive seed layer of substrate
122
with the tips of the contact pins
126
. A power supply (not shown) is attached to pins
126
and is configured to provide an electrical bias to the substrate
122
. The substrate
122
is positioned above the cylindrical electrolyte container
112
and electrolyte flow impinges in a generally perpendicular manner on a substrate plating surface during operation of cell
100
.
However, one problem encountered in utilizing conventional electroplating processes for manufacture of semiconductor devices is that the electrical contacts used to provide the plating bias to the substrate surface contact the production surface of the substrate. Although the contacts are generally positioned about the perimeter of the substrate, i.e., within the outer 2-6 millimeters of the substrate (preferably in the 3-4 millimeter range), and therefore, contact the substrate in the outer 2-6 millimeter band, the contacts nonetheless occupy valuable surface area on the substrate that may be used for production. In a 200 mm substrate, for example, the outer 6 mm band of the substrate that is used to accommodate the contact pins in a conventional electroplating apparatus occupies approximately 6,500 mm
2
, which is surface area on the production surface of the substrate that may be used for device production.
Further, when electrical contacts are placed on the production surface, generally the configuration includes at least one seal that is used to prevent electrolyte from coming into contact with the contact pins, as this causes plating on the contacts and decreases the effectiveness and consistency of the plating apparatus. Therefore, conventional production surface contact configurations require substantial effort to prevent electrolyte from coming into contact with the contact pins. Additionally, the production surface contact pins cause a disturbance of the plating field lines and may trap air bubbles proximate the substrate surface when the substrate is lowered into the electrolyte solution for plating.
Therefore, there exists a need for an apparatus and method for plating substrates using electrical contacts configured to engage the substrate on the non-production surface.
SUMMARY OF THE INVENTION
Embodiments of the invention generally provide an electro-chemical deposition processing cell having a head assembly with a substrate holder and a cathode. An electrolyte container positioned proximate the head assembly and having an anode disposed therein is included, and a power supply in electrical communication with the cathode and the anode is provided. The substrate holder is configured to mechanically and electrically engage a substrate on the non-production side of the substrate during an electroplating process.
Embodiments of the invention further provide an apparatus for securing and electrically contacting a substrate on a non-production surface of the substrate. The apparatus includes a substrate holder assembly having a substrate engaging surface formed thereon, the substrate engaging surface being configured to eng
Lubomirsky Dmitry
Olgado Donald J. K.
Wood Michael
Applied Materials Inc.
Moser Patterson & Sheridan
Valentine Donald R.
LandOfFree
Apparatus and method for electro chemical plating using... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and method for electro chemical plating using..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for electro chemical plating using... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3309885