Apparatus and method for efficiently determining addresses for m

Details Apparatus and method for efficiently determining addresses for m Apparatus and method for efficiently determining addresses for m

1997-05-23

1998-05-12

Moore, David M.

Electrical computers and digital processing systems: memory

Address formation

Slip control, misaligning, boundary alignment

711219, 711220, G06F 1200

Patent

active

057522731

ABSTRACT:
An apparatus and method for efficiently generating the consecutive addresses needed to access misaligned or doubleword length data stored in the memory of a general purpose microprocessor. The apparatus shares the address generation operations between a small 3 bit adder, typically contained in the bus unit, and the execution unit. Control logic is used to determine whether a data misalignment situation exists based on the length of the data which is to be retrieved and the starting address of the data. When misalignment is indicated, the control unit acts to assign the address calculations to either the 3 bit adder alone or the execution unit together with the 3 bit adder depending upon how much the present address must be incremented to obtain the new addresses.

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