Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
1998-08-26
2001-03-20
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S225700
Reexamination Certificate
active
06205063
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to memory devices and specifically to a method and apparatus for efficiently correcting defects in memory arrays.
2. Description of the Related Art
Memory arrays, like other electronic circuit components, are susceptible to manufacturing defects and failure. Memory arrays are typically fabricated on an integrated circuit chip, which may be a dedicated memory chip or may include other circuit components. Defects in a memory array may be caused by fabrication errors or improper handling. Environmental factors, age or improper use can cause a memory array to fail at any time.
As a result, techniques have been developed to correct defects in memory arrays. One attempt at correcting defects in arrays includes designing the array to include redundant memory cells. The redundant cells are employed by selectively blowing fuses within an array of fuses connecting the array of cells after determining which cells are defective. When the memory array is operated, storage information is routed to redundant cell locations based on which fuses are blown. In current designs, the arrangement of fuses is such that particular fuses are dedicated to a particular portions of the memory array. Therefore, in order to allow for correction of cells in different portions of the memory array, multiple fuse groups must be implemented. As a result, the number of fuses increases with the number of potential repairable defects, the number of redundant cells and the number of memory array portions.
Static Random Access Memory (SRAMS) arrays employ Field Effect Transistors (FETs) for memory cells. As technologies continually develop to reduce the size of FETs and logic circuitry, technologies for reducing the size of fuses are not improving as quickly. As a result, the area dedicated for fuses on logic chips is increasing in relation to the area dedicated for logic circuitry.
Therefore, there exists a need for a method and apparatus for correcting defects in memory arrays with minimal increase in circuit area.
SUMMARY OF THE INVENTION
The present invention relates to efficiently correcting defects in memory circuits with minimal increase in circuit area.
In an embodiment of the invention, a memory circuit contains a fuse circuit, a fuse controller and a memory array. After the memory array is tested to determine the locations of defective memory cells within the memory array, a fuse circuit containing a plurality of fuses is “coded” to describe the memory cell location. The fuse circuit contains at least two groups of fuses: a first plurality of fuses that are coded or “blown” to describe a memory cell location within any of several portions of the memory array and a second plurality of fuses coded to indicate the particular portion of the memory array that contains the defective memory cell.
During operation of a memory circuit, the fuse controller forwards the cell location to the memory array portion that has the defective memory cell based on the information coded within the second plurality of fuses. The memory array portion activates a redundant memory cell when an incoming address matches the cell location forwarded by the fuse controller from the fuse circuit. Storage data is stored in the redundant memory cell and not the defective memory cell.
Since fuses are associated with a particular memory array portion after the locations of the defective memory cells are determined, fuses are efficiently allocated to identify the defective memory cells throughout the memory array. The number of fuses can be reduced while still allowing for the correction of defects within the memory array. Therefore, circuit area is efficiently utilized for fuses while still allowing for correction of defective memory cells.
REFERENCES:
patent: 5657280 (1997-08-01), Shin et al.
patent: 5999463 (1999-12-01), Park et al.
Aipperspach Anthony Gus
Levenstein Sheldon Bernard
International Business Machines - Corporation
Le Vu A.
Maxwell Lawrence D.
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