Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1997-08-14
2000-02-29
Wright, Norman Michael
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
714 18, G06F 1300
Patent
active
060322675
ABSTRACT:
A parallel, fault-tolerant computer system in which data is transferred between processes in a single CPU by two methods. In a first method, the data is copied each time it is transferred. In a second method, the data is not copied, but is passed through a shared memory, queueing system. The first method is used to ensure fault-tolerance and linear expandability. The second method is used to minimize the time required for inter-process communication. Use of the shared memory queueing system allows for increased vertical and horizontal modularity for processes executing in a same CPU.
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Chapter 11 Interprocess Communication in Book entitled "Inside 0S/2" by Gordon Letwin published by Microsoft Press, 1988, pp. 151-168.
Clark Thomas Marshall
Fishler Leonard Richard
Compaq Computer Corporation
Wright Norman Michael
LandOfFree
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