Electrical computers and digital data processing systems: input/ – Interrupt processing
Reexamination Certificate
2006-05-30
2006-05-30
Dang, Khanh (Department: 2112)
Electrical computers and digital data processing systems: input/
Interrupt processing
C710S036000, C710S264000
Reexamination Certificate
active
07054972
ABSTRACT:
An apparatus and method for dynamically enabling and disabling interrupt coalescing in a data processing system. The present invention involves consistently monitoring IO load on an IOP of an IO adapter. The firmware on the IO adapter may have a global variable that stores counters for PCI function registers. Each counter tracks the number of outstanding IOs of a corresponding PCI function register. The counter is incremented whenever a new IO is received and is decremented upon posting the completed message back to the OS. A timer interrupt is generated periodically so that an ISR may be periodically performed. In the ISR, the maximum value stored of each counter seen since last timer interrupt is analyzed. When the maximum value stored is greater than a predetermined threshold value, the interrupt coalescing is enabled.
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Besmer Brad D.
Johnson Stephen B.
Parry Owen N.
Dang Khanh
Huynh Kim T.
LSI Logic Corporation
Suiter - West - Swantz PC LLO
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