Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1999-03-16
2001-08-07
Auve, Glenn A. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S243000
Reexamination Certificate
active
06272580
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a computer system and, more particularly, to a device and method for granting accesses to a peripheral bus according to a multi-level prioritization scheme which can elevate or promote a lower level bus master to an upper level prioritization ring if the target of the lower level bus master becomes unavailable or is data transfer from the lower level bus master is interrupted.
2. Description of the Related Art
It is well known that computer systems in general employ a mechanism for allocating a shared resource. That shared resource may involve a bus on which multiple bus agents are connected. The allocation mechanism and its supporting hardware define arbitration protocols by which only one agent at a time can achieve mastership of the common bus.
If an agent wishes to communicate with another agent, the first agent typically sends a signal requesting mastership across the common bus connecting the two agents. The first agent soliciting mastership is often called the bus master, and the agent that responds to that master is called the slave. Some agents can act only as masters, some only as slaves, and others as either masters or slaves.
If many agents attempt to gain access to a common bus at the same time, the arbitration protocol must decide which agent should be given priority. There are many types of arbitration protocols currently used to formulate that decision. For example, arbitration can be performed either in a round-robin fashion or by a fixed priority scheme. Round-robin arbitration involves assigning priority in a cyclical sequence or loop. If two or more agents wish to use the common bus resource, access is granted to the first agent within the loop closest to the last agent which used the common bus resource. Accordingly, a pointer is directed to a port upon the round-robin arbitration ring and thereby points to the last agent to use the bus. The pointer is rotated about the ring of ports each time access is granted. A fixed priority arbitration scheme involves assigning a unique priority to each agent. If two or more agents wish to use the bus resource, access is always granted to the device with the highest priority value. Examples of various round-robin and fixed priority schemes are set forth in U.S. Pat. No. 5,088,024 (herein incorporated by reference).
The fixed priority arbitration principle can advantageously assign a higher priority to agents which must gain access to the bus quickly in order to avoid malfunction or loss of information. Such agents are often referred to as low latency agents. High latency agents, however, can wait for a longer period of time without suffering ill effects. An unfortunate aspect of a fixed priority scheme is that the priority value of each agent is fixed and cannot be readily changed. Conversely, a round-robin arbitration scheme gives equal opportunities to all agents, such that each agent is given a turn at having the highest priority. However, once an agent has terminated its access, it must wait its turn until all the other agents within the ring have culminated their accesses. Agents with low latency may therefore be unfortunately starved of access to the bus.
It would be desirable to introduce a multi-level arbitration mechanism which can assign higher priorities to low latency agents and lower priority to high latency agents. As defined henceforth, the shared resource is a peripheral bus, and the agents are peripheral devices which are operably connected to that bus. The peripheral bus includes a peripheral component interface (“PCI”) bus and peripheral devices include all devices either directly or indirectly coupled to, e.g., the PCI bus. The peripheral devices may therefore entail devices such as the microprocessor which is connected to the peripheral bus through a bus interface unit.
The advantage of introducing a multi-level arbitration system within the confines of a round-robin arbitration scheme would be particularly beneficial if the high and low priority peripheral devices can be dynamically switched between the high and low level priority rings. Accordingly, it would be desirable to introduce a mechanism and method for altering the assignment of peripheral devices from a port upon the low priority ring to a port on the high priority ring during run time. This benefit would more adequately service low priority peripheral devices whose data transfer is somehow interrupted and must thereafter be retried.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by an improved computer system arbitration protocol. The improved protocol entails a multi-level round-robin arbitration scheme which assigns various agents or peripheral devices to either the high priority arbitration ring or the low priority arbitration ring (if two rings are used) during boot-up of the computer system. A configuration register is programmed during boot-up to retain values indicating the high or low priority status of each peripheral device. In addition, the configuration register is programmed to ensure an initial priority within the high and low priority rings. For example, CPU requests are given a higher priority than requests from an Industry Standard Architecture (“ISA”) peripheral device during the initial arbitration sequence of either the high or low priority arbitration rings. The configuration register therefore assigns specific peripheral devices to specific ports on either the high or low priority rings.
It is noted that more than two levels and, therefore, more than two priority rings may be employed if desired. As such, the present arbitration system involves multiple rings, each of which have dissimilar priority from one another.
The high priority ring is designed so that peripheral devices connected to high priority ports will be given priority over any peripheral devices connected to low priority ports within the low priority ring. As such, the devices on the high priority ring will be polled first, with one port reserved on the high priority ring for transitioning to the low priority ring. It is not until after all high priority devices between the high priority pointer and the low priority ring ported on one high priority port will the first low priority device be polled. If the high priority ring involves M number of potential masters then, depending on where the high priority pointer is located, up to M arbitration cycles are needed before priority is given to a low priority device. Once the low priority device access has been completed, then both the high and low priority pointers are advanced one port location. If there are N number of low priority devices assigned to low priority ports then, in a worst case scenario, a low priority device will get access to the bus once every N times M arbitration cycles. Almost all peripheral buses employ a sequence of granting mastership before transferring data. The arbitration cycle must therefore precede a data transfer cycle. Unfortunately, instances may arise during data transfer which can temporarily disrupt that transfer. A procedure known as “retry” is often used as an attempt to re-arbitrate for the bus and, therefore, complete the previously interrupted data transfer. If data transfer to or from a low priority device is interrupted, the low priority device would have to wait up to N times M arbitration cycles before it can regain mastership of the bus during its retry operation. This delay is in most instances unacceptable since data transfer of the low priority device is often a prerequisite for subsequent data transfers of high priority devices. Accordingly, one benefit hereof is to implement a mechanism and methodology for temporarily elevating a low priority device to the high priority ring if its data transfer should become interrupted. In this fashion, the low priority device is given equal status with high priority devices and will be granted access to the bus ahead of its previous counterpart low priority devices. However, since the high priority pointer i
Jones Phillip M.
Lee Peter
Lester Robert A.
Stevens Jeff
Wolford Jeff W.
Auve Glenn A.
Compaq Computer Corp.
Conley & Rose & Tayon P.C.
Daffer Kevin L.
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