Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2000-07-20
2002-04-02
Peikari, B. James (Department: 2186)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S201000, C713S500000, C713S501000, C714S721000
Reexamination Certificate
active
06366514
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a dynamic memory (DRAM) refresh structure. More specifically, the present invention relates to a DRAM refresh structure with two or more clocks for controlling the refresh operations of the memory cells.
2. Description of the Related Art
One conventional DRAM cell has a metal-oxide-semiconductor transistor (MOS) and a capacitor, as show in FIG.
1
.
FIG. 1
illustrates a structure of a conventional DRAM array. A primary problem with DRAM is that DRAM does not store data permanently. Rather, DRAM has to be refreshed. This is because DRAM stores data as a charge on a capacitor. Over time, the charge leaks out of the capacitor. Without a refresh mechanism, data stored in a DRAM is lost. Refresh mechanisms read the contents of a DRAM memory location and restore the data, thereby refreshing the charge on the capacitor. The refresh must occur prior to the time the capacitor discharges. Data retention time is defined by the DRAM manufacture's specification. Refresh time, representing the time interval between two refresh operations for each cell, must be shorter than the data retention time in a DRAM IC.
Refresh is accomplished by accessing the data within each cell in a DRAM. DRAM modules are generally organized in a matrix having rows and columns. In order to effectively perform refresh operations without taking an inordinate amount of time by continuously reading and writing to each cell every couple of milliseconds, DRAMs are organized so that an entire row may be refreshed during a single operation. For example, in order to simultaneously refresh the cells C
0
and C
1
, the word line Xi is selected to turn on the MOSs in the cells C
0
and C
1
. Then, via the bit lines Bj and Bj+1, latch circuits Bj and Bj+1 read the data stored in the capacitors of the cells C
0
and C
1
and respectively restore the data.
FIG. 2
is a conventional memory refresh structure. Cells simultaneously refreshed are grouped as a segment, such as the segments SO
1
-SO
N
shown in FIG.
2
. The conventional memory refresh structure comprises a clock generator
10
and a pointer generator
12
. The clock generator
10
provides a clock signal. According to the clock signal, the pointer generator
12
generates a pointer to select, in a predetermined order, one of the segments and refresh the cells in the selected segment.
The clock generator
10
and the pointer generator
12
are designed to refresh the cells within the data retention time provided by the specification. For example, if the specification of a DRAM IC shows a data retention time of 4 ms and if the number of the segments is 256, then the time interval of the clock signal should not be longer than 4 ms/256~15 us. That means the pointer generated by the pointer generator
12
may sequentially and cyclically select the segments SO
1
-SO
256
with a time step of 15 us to repetitively refresh the cells with a refresh time of 4 ms. Therefore, the data stored in the cells can be kept.
However, cells will sometimes fail to keep data longer than the shortest discharge time defined in the specification, thereby causing the IC to fail. One way to prevent IC failure is by Presetting redundant cells to replace failed cells. However, if the number of failed cells is greater than that of redundant cells and the IC has no further repair structure, the IC will definitely fail.
FIG. 3
illustrates a testing result of a 16 Mbit DRAM IC. The horizontal coordinate represents the varied refresh time, and the vertical coordinate represents the total number of bits with lost data. The frequency of the clock signal can be controlled by signals from an external tester to vary the refresh time for the cells. Suppose the specification defines a data retention time of 4 ms. As shown in
FIG. 3
, some of the cells still lose the stored data and cause IC failure.
As the technology has progressed, the total number of the cells in an IC has become as large as several million. It is wasteful to discard a DRAM IC just because few cells fail among such a large amount of cells. More specifically, it is uneconomical to abandon a logical IC of embedded DRAM having a functional periphery circuit because a few failed cells are found inside.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a novel refresh structure that prevents IC failure. The refresh structure provided by the present invention can utilize cells that would normally be classified as failed in the prior art.
The present invention achieves the above-indicated objects by providing a memory refresh structure. The memory refresh structure has an original clock generator, a first clock generator, a memory array, an original segment pointer generator, and a first segment pointer generator. The original clock generator periodically generates an original clock signal. The first clock generator periodically generates a first clock signal. The memory array is composed by a plurality of memory cells, which are grouped into a plurality of original memory segments. According to the original clock signal, the original segment pointer generator generates an original pointer to cyclically select, in a predetermined order, one of the original memory segments and trigger refresh operations for the memory cells in the selected original memory segment. The first segment pointer generator one-to-one tags a portion of the original memory segments as first memory segments. According to the first clock signal, the first segment pointer further generates a first pointer to cyclically select, in a predetermined order, one of the first memory segments, and trigger refresh operations for the memory cells in the selected first memory segment. An original refresh time, defined as the time interval between two refresh operations for each cell in the original memory segments, is longer than a first refresh time, defined as the time interval between two refresh operations for each cell in the first memory segments.
The major advantage of the present invention that cells in the first memory segments, which would have been defined as failures in the prior art, are utilizable, thereby improving the IC yield rate.
REFERENCES:
patent: 4594656 (1986-06-01), Moffet
patent: 4985868 (1991-01-01), Nakano et al.
patent: 5349562 (1994-09-01), Tanizaki
patent: 5465367 (1995-11-01), Reddy et al.
patent: 5566117 (1996-10-01), Okamura et al.
patent: 5583823 (1996-12-01), Park
patent: 5818777 (1998-10-01), Seyyedy
Darby & Darby
Peikari B. James
Taiwan Semiconductor Manufacturing Co. LTD
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