Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Patent
1996-08-16
1998-06-02
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
711163, G06F 1200
Patent
active
057617031
ABSTRACT:
A dynamic memory refresh apparatus includes a programmable refresh interval generator that generates an interval for generating a refresh request signal. The refresh interval time is based on the manufacturer specified DRAM cycle time, the system clock period, and the number of memory segments on the memory board that are supported by the computer system. The refresh interval time substantially maximizes the time between refreshes of a particular DRAM module. The dynamic refresh apparatus also includes a memory segment pointer generator that generates a memory segment pointer. The memory segment pointer points to the next memory segment to be refreshed. The memory segment pointer is generated such that the memory segments are selected in a staggered manner. In addition, the dynamic memory refresh apparatus includes a refresh request generator that generates a refresh request signal for the memory segment pointed to by the memory segment pointer. The refresh request generator generates the refresh request only for segments for which data is present.
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King , Jr. Conley B.
Sowell, Esq. John B.
Starr, Esq. Mark T.
Swann Tod R.
Unisys Corporation
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