Computer graphics processing and selective visual display system – Computer graphics display memory system – Graphic display memory controller
Reexamination Certificate
2000-06-23
2004-09-14
Tung, Kee M. (Department: 2676)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Graphic display memory controller
C345S531000, C345S537000, C345S565000
Reexamination Certificate
active
06791555
ABSTRACT:
TECHNICAL FIELD
The present invention is related generally to the field of computer graphics, and more particularly, to a memory system for use in a computer graphics processing system.
BACKGROUND OF THE INVENTION
A heterogeneous memory system is a memory system where several different memories, or levels of memory, are used to satisfy memory demands of an computer application. An example of an application for a heterogeneous memory system is in graphics processing systems. Different levels of memory are used by a graphics processing system to facilitate graphics processing and rendering of graphics images on a display. A first level of memory is typically embedded memory that is fabricated directly on the same semiconductor substrate as a graphics processor. Embedded memory can provide data to the graphics processor at very low access times, and consequently, increase the speed at which graphics data may be processed. A second level of memory is typically memory that is external to the device, but located on the same graphics card as the graphics processor. Memory such as this is commonly referred to as external, or local memory. A third level of memory is AGP memory, or host memory that the graphics processor can access through a system bus. Host memory generally has the greatest access time of the three levels of memories because the graphics processor can only access the AGP memory via a system bus and several different memory and bus controllers. Although local memory can provide data more quickly than the host memory, it still is considerably slower than the embedded memory of the first level of memory.
For a conventional heterogeneous memory system, there are two typical arrangements. A first example of a heterogeneous memory system is arranged with a single memory controller to handle all memory accesses. Such an arrangement is illustrated in FIG.
1
. The memory system
10
includes a central memory controller
12
coupled to both memory
20
through memory bus
16
, and memory
22
through memory bus
18
. The memory
20
may be representative of embedded memory, and the memory
22
may be representative of external memory. In operation, the central memory controller
12
receives memory access requests from various requesting entities, such as a graphics processor, over buses
14
a-n
. The central memory controller
12
services the various memory access requests by determining whether the requested memory address is located in the memory
20
or the memory
22
. The appropriate memory device is accessed and data is written to or read therefrom. An arrangement such as memory system
10
has the advantage that additional memory may be easily added because all memory access requests are serviced by the central memory controller
12
. For the same reason, the various memory access requests can all be handled seamlessly by the central memory controller
12
. That is, when a memory access request is made, only the central memory controller
12
must determine which memory, either memory
20
or memory
22
, to access. However, a problem with the arrangement of memory system
10
is that there are physical limitations as to the number of buses
14
a-n
that may be routed to the memory controller
12
. Additionally, as the complexity of the central memory controller
12
increases to accommodate a greater number of memory access requests, the amount of space the central memory controller occupies also increases. Thus, space overhead issues become a concern in applications where small graphics processing systems are desired.
A second example of a heterogeneous memory system is shown in FIG.
2
. Memory system
30
addresses some of the concerns raised by the memory system
10
of FIG.
1
. The memory system
30
includes a central memory controller
12
coupled to a memory
20
through a memory bus
16
. The central memory controller
12
services only the memory access requests made to memory
20
. The memory system
30
also includes memory
22
directly coupled to a requesting entity through memory bus
32
. Thus, memory access requests to memory
22
may be only made over the memory bus
32
. The memory
20
may represent embedded memory, while the memory
22
may represent local memory. As illustrated in
FIG. 2
, all memory access requests to memory
20
are controlled by the central memory controller
12
. However, access to the memory
22
, is controlled directly by the requesting entity coupled to the bus
32
. That is, access to memory
22
can be made only by the requesting entity hardwired to the bus
32
.
The memory system
30
does, to some degree, resolve the issues with regards to the physical limitations of routing a plurality of request lines to a single central memory controller, as well as space overhead issues resulting from the complexity of using a central memory controller. However, a problem with the memory system
30
is that the allocation of available memory is fixed according to the design of the circuitry. That is, the memory
22
may be accessed only by the requesting entity to which it is coupled through bus
32
. Any available memory in the memory
22
cannot be reallocated for another purpose, such as storing overflow data from the memory
20
. Furthermore, memory access requests must be delegated prior to being made either to the central memory controller
12
or the memory
22
, rather than having all memory access requests simply handled by a single central memory controller. Moreover, adding additional memory to the memory system
30
is made more difficult by the fixed arrangement. Additional memory cannot simply be reallocated, but must be added to supplement either memory
20
or memory
22
, but not both.
Therefore, there is a need for a memory system where the number of memory access request lines to a memory controller is reduced and where the available memory may be allocated efficiently.
SUMMARY OF THE INVENTION
The present invention relates to a distributed memory controller memory system for a graphics processing system having addressable memory areas, each of which is coupled to a respective memory controller. Each memory controller accesses the addressable memory area to which it is coupled. The memory controllers are further coupled to each other through a memory controller bus upon which a memory access request and data may be passed from one memory controller to other memory controller. A memory access request to a memory location in one addressable memory area, but received by a memory controller coupled to another addressable memory area, is passed through the memory controller bus from the receiving memory controller to the memory controller coupled to the addressable memory area in which the requested location is located in order to service the memory access request. Additional addressable memory areas coupled to a respective memory controller may also be included in the memory system. The additional memory controllers are also coupled to the memory controller bus in order to receive and pass memory access requests from the other memory controllers. The addressable memory locations may be defined by values stored in registers in the respective memory controller in order for the memory controller to determine whether the requested location is within the memory area to which it is coupled.
REFERENCES:
patent: 4507730 (1985-03-01), Johnson et al.
patent: 5357621 (1994-10-01), Cox
patent: 6252512 (2001-06-01), Jaddeloh
Peterson James R.
Radke William
Dorsey & Whitney LLP
Nguyen Hau
Tung Kee M.
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