Computer graphics processing and selective visual display system – Computer graphics display memory system – Addressing
Reexamination Certificate
1997-12-29
2002-03-26
Chauhan, Ulka J. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Addressing
C345S531000, C345S537000, C345S546000, C345S560000, C348S718000
Reexamination Certificate
active
06362827
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an address generating apparatus, a picture display apparatus, an address generating method and a picture displaying method used in a graphics computer, a special effect device or a video game machine which are picture equipments employing a computer.
2. Related Art
In a picture display apparatus having a picture memory, such as a personal computer or a television game machine, data written in the picture memory is read out in accordance with synchronization signals of, for example, the NTSC (National Television System Committee) system.
Such picture display apparatus includes a cathode ray tube controller (CRTC)
302
for generating pre-set addresses based on synchronization signals generated by a synchronization signal generating circuit
301
, a VRAM
303
for reading out one-frame picture data based on addresses designated by the CRTC
302
and a D/A converter
305
for converting frame data supplied via a line buffer
304
into analog data, as shown for example in FIG.
1
.
The CRTC
302
includes a horizontal synchronization counter
311
for counting horizontal synchronization signals, a horizontal resolution reducing circuit
312
for lowering the horizontal resolution to a pre-set value in case of necessity, a horizontal slicing circuit
313
for starting slicing horizontal scanning lines, and a summation circuit
314
for summing data from the horizontal resolution reducing circuit
312
and the horizontal slicing circuit
313
.
In addition, the CRTC
302
includes a vertical synchronization counter
316
for counting the vertical synchronization signals, a vertical resolution reducing circuit
317
for lowering the vertical resolution to a pre-set value in case of necessity, a vertical slicing circuit
318
for starting slicing vertical scanning lines, a summation circuit
319
for summing data from the vertical resolution reducing circuit
317
and the vertical slicing circuit
318
and an address generating circuit
320
for generating addresses based on the horizontal synchronization signals and the vertical horizontal synchronization signals supplied thereto.
In the above-described picture display apparatus, the synchronization signal generating circuit
301
generates the horizontal synchronization signals and the vertical horizontal synchronization signals which are sent to the CRTC
302
.
In the CRTC
302
, the horizontal synchronization counter
311
counts the horizontal synchronization signals supplied from the synchronization signal generating circuit
301
.
The horizontal resolution reducing circuit
312
reduces the number of the horizontal synchronization signals, if necessary, for lowering the horizontal resolution of picture data read out from the VRAM
303
.
When a pre-set timing is reached by the counting of the horizontal synchronization signals by the horizontal synchronization counter
311
, the horizontal slicing circuit
313
generates horizontal slicing data for slicing at a pre-set position of the horizontal scanning line and transmits the horizontal slicing data to the summation circuit
314
.
The summation circuit
314
superimposes the horizontal slicing data on the supplied horizontal synchronization signals and transmits the superimposed data to the address generating circuit
320
.
On the other hand, the vertical resolution reducing circuit
316
counts the vertical synchronization signals from the synchronization signal generating circuit
301
.
The vertical resolution reducing circuit
317
reduces the number of the vertical synchronization signals, if need be, for lowering the vertical resolution of picture data read out from the VRAM
303
.
When a pre-set timing is reached by the counting of the vertical synchronization signals by the vertical synchronization counter
318
, the vertical slicing circuit
318
generates vertical slicing data for slicing at a pre-set position of the vertical scanning line and transmits the vertical slicing data to the summation circuit
314
.
The summation circuit
319
superimposes the vertical slicing data on the supplied horizontal synchronization signals and transmits the superimposed data to the address generating circuit
320
.
The address generating circuit
320
generates addresses associated with the superimposed data supplied thereto and transmits the resulting addresses to the VRAM
303
.
The VRAM
303
sends the picture data associated with the supplied addresses via line buffer
304
to the D/A converter
305
.
The D/A converter
305
converts the supplied picture data into analog data for outputting video signals.
Thus, the picture data written in the VRAM
303
is directly displayed via CRTC
302
on a display screen.
However, if frame data including plural pictures are written in the VRAM
303
, it has not been possible with the CRTC
302
employed in the above-described picture display apparatus to slice the plural pictures to display the sliced pictures at a desired location on a sole screen.
Moreover, it has not been possible with the CRTC
302
to receive plural picture data supplied from outside to display the received picture data on the screen.
In view of the above-depicted status of the art, it is an object of the present invention to provide an address generating apparatus, a picture display apparatus, an address generating method and a picture display method, whereby plural pictures can be displayed at plural locations on a sole screen and whereby a picture supplied externally can also be received and displayed thereon.
SUMMARY OF THE INVENTION
An address generating apparatus according to the present invention includes address generating means for generating addresses for reading out picture signals written in a picture memory based on synchronization signals, a plurality of buffers respectively supplied with picture signals read out from the picture memory based on the addresses and controlling means for independently controlling the picture signals outputted by the buffers so that the picture signals supplied to the buffers will be displayed on a sole screen.
In the address generating apparatus according to the present invention, at least one of the buffers preferably receives picture signals supplied from external data to route the recieved picture signals to the picture memory.
A picture displaying apparatus according to the present invention includes address producing means having address generating means for generating addresses for reading out picture signals written in a picture memory based on synchronization signals, a plurality of buffers respectively supplied with picture signals read out from the picture memory based on the addresses, and controlling means for independently controlling the picture signals outputted by the buffers so that the picture signals supplied to the buffers will be displayed on a sole screen, and synthesizing means for synthesizing picture signals outputted by the buffers.
In the picture displaying apparatus according to the present invention, preferably at least one of the buffers receives picture signals supplied from external data to route the received picture signals to the picture memory.
In the picture displaying apparatus according to the present invention, preferably the synthesizing means is program-controlled based on pre-set calculations by the control means.
The picture displaying apparatus according to the present invention preferably includes one or more cache memories fed with picture signals read out from the picture memory for writing supplied picture signals. The control means sequentially read-out controls the picture signals written in the cache memory for causing a plurality of pictures of the same sort to be displayed on a sole screen.
In the picture displaying apparatus according to the present invention, the buffer preferably is made up of a line memory.
An address generating method according to the present invention includes generating addresses for reading out picture signals written in a picture memory based on synchronization signals
Chauhan Ulka J.
Fulwider Patton Lee & Utecht LLP
Sony Computer Entertainment Inc.
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