Apparatus and method for dispatching very long instruction...

Electrical computers and digital processing systems: processing – Processing architecture – Long instruction word

Reexamination Certificate

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Details

C712S206000, C712S213000

Reexamination Certificate

active

07366874

ABSTRACT:
Apparatus and method for dispatching a very long instruction word (VLIW) instruction having a variable length are provided. The apparatus for dispatching a VLIW instruction includes a packet buffer for storing at least one or more VLIW instructions, and a decoding unit configured to constitute a VLIW instruction to be currently executed among the VLIW instructions stored in the packet buffer and decode predetermined bits of each sub-instruction contained in the VLIW instruction. The apparatus dispatches a corresponding sub-instruction to an FU which corresponds to each sub-instruction, based on the results of decoding performed in the decoding unit, position information on the sub-instructions that are placed on the packet buffer, and position information on the sub-instructions that are placed in the current VLIW instruction. Sub-instructions can be effectively dispatched to corresponding FUs using simple decoding logic even in a case where the length of the VLIW instruction is not fixed.

REFERENCES:
patent: 5761506 (1998-06-01), Angle et al.
patent: 5958044 (1999-09-01), Brown et al.
patent: 6061786 (2000-05-01), Witt
patent: 6122722 (2000-09-01), Slavenburg
patent: 6173389 (2001-01-01), Pechanek et al.
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patent: 0962856 (1999-12-01), None
patent: 1102165 (2001-05-01), None
patent: 09-167093 (1997-07-01), None
patent: 0104765 (2001-01-01), None
English translation of JP 09-167093.

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