Electrical computers and digital processing systems: memory – Address formation – Address mapping
Patent
1997-02-27
1999-09-28
Gossage, Glenn
Electrical computers and digital processing systems: memory
Address formation
Address mapping
711202, 395888, G06F 1210
Patent
active
059604654
ABSTRACT:
A method and apparatus for directly accessing data compressed by a dictionary-based compression scheme are disclosed. The apparatus may include an execution unit for processing data and an address generation unit connected to the execution unit for generating a logical address corresponding to the data. A compressed memory address translation unit operably connected to the address generation unit maps the logical address to a linear address corresponding to a physical address at which the data is stored as compressed data. The compressed memory address translation unit may include comparison elements. Each comparison element is adapted to determine whether an input address is within an address range associated therewith. Each comparison element may further include a map logic circuit for computing the linear address as an offset and a base linear address. One single comparison element uniquely provides the linear address to be output by the compressed memory address translation unit. A memory device may store a compression descriptor table comprising memory descriptors. The compression descriptor table may comprise both local and global tables mapping logical address ranges to physical address ranges within the memory device, with each descriptor including a logical address, a length, and a linear address. Each descriptor relates a unique logical address range (corresponding to a portion of a logical address space), to a physical address range (corresponding to space in the memory device).
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Gossage Glenn
Novell Inc.
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