Electric lamp and discharge devices: systems – Cathode ray tube circuits – Cathode-ray deflections circuits
Reexamination Certificate
1998-11-16
2001-03-27
Ham, Seungsook (Department: 2878)
Electric lamp and discharge devices: systems
Cathode ray tube circuits
Cathode-ray deflections circuits
C315S368130, C348S806000
Reexamination Certificate
active
06208092
ABSTRACT:
BACKGROUND OF THE INVENTION
In conventional cathode ray tube deflection processing, analog signals are used to control the current provided to a deflection coil and to control the voltage applied to a focus grid. However, the analog technique is limited by a distortion phenomenon generated in an irregular shape due to flattening of the screen of the cathode ray tube (CRT) and generated by a deflection yoke coil. Control of such phenomena is complicated and difficult to fine tune. A plurality of control terminals are required in order to elaborately and minutely correct the distortion phenomenon. In addition, a well-known phenomenon referred to as north-south (NS) pincushion distortion is uncorrectable, and an additional tilt correcting coil is required for correcting tilt.
Furthermore, in conventional analog deflection devices, electric high tension (EHT) is evenly maintained regardless of the amount of beam in order to correct distortion due to the EHT fluctuation, resulting in increased manufacturing expenses.
In computer CRT applications, the frequencies of horizontal and vertical synchronous signals provided to the cathode ray tube can vary over a wide range. For example, the frequency of the horizontal synchronous signal input to the deflection processing device can vary from 15 kHz to 120 kHz, according to the video output mode of the computer, for example VGA mode or SGA mode. Processing of signals over such a wide range is hardware intensive. Moreover, when the frequencies of horizontal synchronous signals vary over a wide range, a Moire phenomenon is produced, in which the colors of the displayed screen spread like a wave.
SUMMARY OF THE INVENTION
The present invention is directed to a deflection processing device for a cathode ray tube, employed for example in a television set, an oscilloscope, a character display unit, or an image display unit. In particular, the present invention is directed to a digital deflection processing device and method for digitally processing the deflection of the cathode ray tube, in a manner which addresses the limitations of conventional techniques.
It is a first object of the present invention to provide a digital deflection processing device for a cathode ray tube for digitally and programmably correcting distortion.
It is a second object of the present invention to provide a phase difference detector in a digital deflection processing device for a cathode ray tube for precisely detecting the phase difference between a reference signal synchronized with a system clock signal and a comparison signal asynchronous with respect to the system clock signal.
It is a third object of the present invention to provide an apparatus and method for stabilizing the jitter of a synchronous signal in a digital deflection processing device for the cathode ray tube.
It is a fourth object of the present invention to provide a method for calculating an interpolation value with respect to X and Y axis coordinate values, performed in the digital deflection processing device for the cathode ray tube.
It is a fifth object of the present invention to provide an interpolation value calculating device for performing the interpolation value calculating method of the fourth object.
To achieve the first object, a digital deflection processing apparatus comprises synchronous and clock signal generating unit for selecting either a first composite synchronous signal extracted from a composite video broadcasting signal or at least one externally-generated second composite synchronous signal in response to a synchronous control signal, outputting the selected signal as a third composite synchronous signal, and generating a main clock signal; synchronous signal phase converting unit for lagging or leading the phase of the third composite synchronous signal corresponding to a first predetermined value and outputting the lagged or lead third composite synchronous signal as a deflection composite synchronous signal comprising a deflection synchronous signal and a deflection vertical synchronous signal; coordinate value generating unit for performing counting, synchronized with the deflection composite synchronous signal, operating the counting result with second predetermined values, and outputting the operation result as the X and Y axis coordinate values of the beam; selection signal generating unit for processing the counting result to generate first through Eth selection signals; horizontal drive signal generating unit for determining the rising and falling edges of a horizontal drive signal using a phase difference between a fly back pulse and the horizontal drive signal, the deflection horizontal synchronous signal, the horizontal correcting signal, and a predetermined duty value; interpolation value calculating unit for calculating distortion correcting functions
8
F(X) through F(Y)], for example by the time division method, in response to the first through Eth selection signals, calculating the respective interpolation values of the X and Y axis coordinate values using the distortion correcting functions, and outputting the calculated interpolation values as the horizontal correct signal, a dynamic focus signal, a vertical sawtooth drive signal, or an east-west distortion compensation signal EWI, according to the relationship:
F
(
X
)=
s
0
f
0
(
X
)+
s
1
f
1
(
X
)+ . . . +
s
n
f
n
(
X
)
F
(
Y
)=
s
0
f
0
(
Y
)+
s
1
f
1
(
Y
)+ . . . +
s
n
f
n
(
Y
)
wherein, S
0
through S
n
represent seed values and ƒ
0
(X) through ƒ
0
(X) and ƒ
n
(X) through ƒ
n
(Y) represent lagrange functions; output adjusting unit for adjusting the gains of the vertical sawtooth drive signal and the EW
1
signal using a voltage obtained by distributing the electric high tension (EHT) of the cathode ray tube, a corresponding value among second predetermined values, and third predetermined values and outputting the vertical sawtooth drive signal and the EW
1
the gains of which are adjusted; and controlling unit for outputting the synchronous control signal, the seed values, the second predetermined values, and the third predetermined values.
The third composite synchronous signal preferably comprises a third horizontal synchronous signal and a third vertical synchronous signal and the main clock signal is preferably output to the synchronous signal phase converting unit, the coordinate value generating unit, the selection signal generating unit, the horizontal drive signal generating unit, the interpolation value calculating unit, and the output adjusting unit.
To achieve the second object, a phase difference detecting apparatus is provided in a digital deflection processing apparatus for a cathode ray tube for digitally performing deflection processing. The apparatus preferably comprises precise phase difference detecting unit for dividing a period of the system clock signal into N sections, where N is an integer not less than 2, detecting a section to which an asynchronous comparison signal is input among the N divided sections, and outputting the value assigned to the detected section as the decimal value of a phase difference between a reference signal synchronized with the system clock signal and the comparison signal; second phase difference detecting unit for detecting the integer value of the phase difference using the system clock signal and the reference signal, and outputting the decimal and the integer value in response to the system clock signal and the comparison signal; and a loop filter for stabilizing the jitter of the integer value using the filtered decimal value and outputting the integer value, the jitter of which is stabilized and which is filtered, as the phase difference.
To achieve the third object, a digital deflection processing apparatus for a cathode ray tube is provided, having a counter for performing counting in response to a counting signal and being reset in response to a synchronous signal the jitter of which is stabilized. The apparatus comprises a window forming portion for outputting the m
Ham Seungsook
Samsung Electronics Co,. Ltd
Samuels , Gauthier & Stevens, LLP
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