Electrical computers and digital processing systems: memory – Address formation – Address mapping
Patent
1994-11-14
1998-10-13
Bowler, Alyssa H.
Electrical computers and digital processing systems: memory
Address formation
Address mapping
711 2, 711201, 36473601, 364737, 36476002, 36478603, 371 215, 371 4011, G06F 1202
Patent
active
058227865
ABSTRACT:
Dedicated parallel comparators perform expand up or expand down segment limit checks for memory accesses. A first three-input comparator has as inputs the complement of the segment limit, the effective address of the first byte of the access, and an configurable third input. For expand up segments, the configurable third input is set to one less than the memory access size. A carry out of the first comparator is generated, and thereby a limit fault indicated, if the address of the last byte of the access exceeds the segment limit. For expand down segments, the configurable third input is set to zero. In this case, the lack of a carry out of the first comparator indicates that the address of the first byte of the access exceeds the segment limit. For expand down segments a parallel second two-input comparator is also used. The second comparator has as inputs the effective address and a hybrid second input. A least significant portion of the hybrid input is set to one less than the memory access size. Multiple bits in a most significant portion of the hybrid input reflect the complement of the segment descriptor's B-bit. The second comparator generates a carry whenever the address of the last byte of the memory access wraps the segment's maximum address value. For expand down segments, a limit fault is indicated by the logical OR of the complement of the first comparator's carry out with the carry out of the second comparator.
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Sowadsky Elliot A.
Widigen Larry
Advanced Micro Devices , Inc.
Bowler Alyssa H.
Follansbee John I.
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